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US4388541A
Expired / Lapsed
US
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Circuit arrangement with MOS-transistors for the rapid evaluation of the logic state of a sampling node
Assignee: Siemens AG
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Filing: 1980-07-23
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Granted: 1983-06-14
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Expires: 2000-07-23
Abstract
Abstract Circuit having MOS-transistors for the rapid evaluation of the logic state of a sampling node, including a circuit input connected to the sampling node, a circuit output, a supply voltage source, an inverter being connected to the circuit input and having an output, a first transistor being connected between the circuit input and the circuit output and having a gate connected to the output of the inverter, a second transistor being connected between the supply voltage source and the circuit output and having a gate connected to the output of the inverter, and a third transistor shunted across the second transistor as a load resistor.
Inventors
- 👤 Burkhard Giebel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 03:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C16/00; G11C16/02; G11C16/06; G11C16/26
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
105 words
Circuit having MOS-transistors for the rapid evaluation of the logic state of a sampling node, comprising a circuit input connected to the sampling node, a circuit output, a supply voltage source, an inverter being connected to said circuit input and having an output, a first transistor being connected between said circuit input and said circuit output and having a gate connected to said output of said inverter, a second transistor being connected between said supply voltage source and said circuit output and having a gate connected to said output of said inverter, and a third transistor shunted across said second transistor as a load resistor.
Claim 2
Dependent Claim
105 words
Circuit having MOS-transistors for the rapid evaluation of the logic state of a sampling node, comprising a circuit input connected to the sampling node, a circuit output, a supply voltage source, an inverter being connected to said circuit input and having an output, a first transistor being connected between said circuit input and said circuit output and having a gate connected to said output of said inverter, a second transistor being connected between said supply voltage source and said circuit output and having a gate connected to said output of said inverter, and a third transistor shunted across said second transistor as a load resistor.
Claim 3
Dependent Claim
25 words
Circuit according to claim 1, including a semiconductor read-only memory array with the sampling node selectively connected to single memory cells, as a read amplifier.
Claim 4
Dependent Claim
26 words
Circuit according to claim 2, wherein said inverter includes transistors of the enhancement type, and said first, second and third transistors are of the enhancement type.
Claim 5
Dependent Claim
31 words
Circuit according to claim 2, wherein said inverter includes an MOS-transistor of the depletion type connected as a load resistor, and said third transistor is an MOS-transistor of the depletion type.
Claim 6
Dependent Claim
23 words
Circuit according to claim 1, wherein said inverter comprises two series-connected transistors, said output of said inverter being connected between said series-connected transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-13 | 1986-12-13 | 1987-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-13 | 1990-12-13 | 1991-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-13 | 1994-12-13 | 1995-06-14 | $7700.00 | Window Closed / Lapsed |