Dynamic semiconductor memory device with decreased clocks

Claim 2

A dynamic semiconductor memory device comprising: a memory cell; a bit line operatively connected to said memory cell; a sense amplifier having a first input operatively connected to said bit line, having a second input and having a ground side input; and a pull up circuit, operatively connected to said bit line and said sense amplifier, including: a capacitor; a first switching transistor operatively connected between a power supply and said bit line and having a gate operatively connected to said capacitor; and a second switching transistor operatively connected between the gate of said first switching transistor and the ground side input of said sense amplifier, operatively connected to said capacitor and having a gate operatively connected to the second input of said sense amplifier.

Claim 3

A dynamic semiconductor memory device as claimed in claim 1, wherein said dynamic semiconductor memory device is operatively connectable to receive a clock signal and wherein said capacitor is operatively connectable to receive the clock signal.

Claim 4

A dynamic semiconductor memory device comprising: a plurality of dynamic memory cells arranged in a matrix and divided into two groups; a pair of bit lines, each of which is operatively connected to a different group of said plurality of dynamic memory cells; a sense amplifier operatively connected to said pair of bit lines and having a ground side; and a pull up circuit, operatively connected to said pair of bit lines, for charging up said pair of bit lines; said pull up circuit comprising: a pair of capacitors each associated with one of said pair of bit lines; a pair of first switching transistors, respectively connected between a power supply line and said pair of bit lines, for charging up said pair of bit lines, each of the transistors of said pair of first switching transistors having a gate, operatively connected to a respective one of said pair of capacitors, and being associated with one of said pair of bit lines; and a pair of second switching transistors, respectively connected between the gates of said pair of first switching transistors and the ground side of said sense amplifier, and each operatively connected to a respective one of said pair of capacitors, for respectively controlling the gate potentials of said pair of first switching transistors, each of the transistors of said pair of second switching transistors having a gate and being associated with the same one of said pair of bit lines as the first switching transistor connected thereto, each gate of said pair of second switching transistors being connected to the non-associated bit line.

Claim 5

A dynamic semiconductor memory device comprising: a plurality of dynamic memory cells arranged in a matrix and divided into two groups; a pair of bit lines, each of which is operatively connected to a different group of said plurality of dynamic memory cells; a sense amplifier operatively connected to said pair of bit lines and having a ground side; and a pull up circuit, operatively connected to said pair of bit lines, for charging up said pair of bit lines; said pull up circuit comprising: a pair of capacitors each associated with one of said pair of bit lines; a pair of first switching transistors, respectively connected between a power supply line and said pair of bit lines, for charging up said pair of bit lines, each of the transistors of said pair of first switching transistors having a gate, operatively connected to a respective one of said pair of capacitors, and being associated with one of said pair of bit lines; and a pair of second switching transistors, respectively connected between the gates of said pair of first switching transistors and the ground side of said sense amplifier, and each operatively connected to a respective one of said pair of capacitors, for respectively controlling the gate potentials of said pair of first switching transistors, each of the transistors of said pair of second switching transistors having a gate and being associated with the same one of said pair of bit lines as the first switching transistor connected thereto, each gate of said pair of second switching transistors being connected to the non-associated bit line.

Claim 6

A dynamic semiconductor memory device as claimed in claim 3, wherein said dynamic memory device is operatively connected to receive a clock signal, wherein each of said pair of capacitors comprises first and second electrodes, each of said first electrodes being connected to the gate of one of said pair of first switching transistors, and each of said second electrodes operatively connectable to receive the clock signal.

Claim 7

A dynamic semiconductor memory device as claimed in claim 4, wherein one of the transistors said pair of first switching transistors is operatively connected to one of the bit lines of said pair of bit lines, and one of said second switching transistors, the gate of which is connected to the non-associated bit line of said pair of bit lines, said first and second switching transistors being turned on and off, respectively, for charging up the associated bit line, when said clock signal is received.