US4386459A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrical measurement of level-to-level misalignment in integrated circuits
Assignee: AT&T Inc
•
Filing: 1980-07-11
•
Granted: 1983-06-07
•
Expires: 2000-07-11
Abstract
Abstract At least one chip on a multiple-chip integrated circuit wafer is dedicated for use as a test device for checking mask level-to-level misalignment. The test device is made during the same fabrication sequence in which the circuit-containing chips are made. No additional processing steps are required for the test device. By forming unique S-shaped members in each test device and establishing electrical contact therewith, a sensitive electrical tester is provided for indicating level-to-level registration in the circuit-containing chips.
Inventors
- 👤 David M. Boulin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:46
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; H; H10; H10P; H10P74/00; H10P74/27; H10P74/277; H10P74/20; H10P74/203; Y; Y10; Y10S; Y10S438/00; Y10S438/975
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
125 words
A method of making an integrated circuit comprising the steps of: fabricating at least one integrated circuit at one or more respective chip sites of a semiconductor wafer in accordance with a specified process sequence, said sequence involving forming an insulating layer between patterned upper and lower conductive layers, at least one other site on said wafer being dedicated for alignment test purposes, and forming an insulating layer between upper and lower conductive layers at each test site in the same respective steps in which said layers are formed at each chip site, wherein the improvement comprises forming at each test site at the level of one of said conductive layers two S-shaped conductive test members disposed at 90 degrees with respect to each other.
Claim 2
Independent Claim
125 words
A method of making an integrated circuit comprising the steps of: fabricating at least one integrated circuit at one or more respective chip sites of a semiconductor wafer in accordance with a specified process sequence, said sequence involving forming an insulating layer between patterned upper and lower conductive layers, at least one other site on said wafer being dedicated for alignment test purposes, and forming an insulating layer between upper and lower conductive layers at each test site in the same respective steps in which said layers are formed at each chip site, wherein the improvement comprises forming at each test site at the level of one of said conductive layers two S-shaped conductive test members disposed at 90 degrees with respect to each other.
Claim 3
Dependent Claim
71 words
A method as in claim 1 wherein the improvement further comprises forming at each test site a plurality of windows in the insulating layer to permit electrical contact to said S-shaped conductive test members, said windows being formed in the same step in which windows are formed at said circuit chip sites, and detecting misalignments of the windows by determining the distances along the S-shaped conductive test members between successive windows.
Claim 4
Dependent Claim
46 words
A method as in claim 2 wherein the improvement further comprises determining said distances by establishing a current flow through the entire serial extent of each of said S-shaped conductive members at each test site and measuring the voltage drops along said members between successive windows.
Claim 5
Dependent Claim
53 words
A method as in claim 3 wherein the improvement further comprises forming the S-shaped conductive test members at each test site in the same step in which the lower conductive layer is formed at said circuit chip sites, and adjusting the process sequence for subsequent wafer fabrication as indicated by said measured voltages.
References Cited (Backward Citations)
US3835530A
Cited
US3650020A
Cited
US3808527A
Cited
US3983479A
Cited
US4144493A
Cited
JPS5434787A
Cited
US4257825A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-06 | 1986-12-06 | 1987-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-06 | 1990-12-06 | 1991-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-06 | 1994-12-06 | 1995-06-07 | $7700.00 | Window Closed / Lapsed |