Synchronization signal separating circuit

Claim 2

A synchronization signal separating circuit for deriving synchronization signals from a composite video signal comprising: a reference voltage source which generates a predetermined reference voltage, a clamp circuit means which receives the composite video signal and a reference voltage from said reference voltage source, and clamps the sync chip level of the composite video signal to said reference voltage level, a detection circuit means, responsive to the clamped composite video signal from said clamp circuit means and a pulse signal applied thereto, for detecting and holding the voltage of the back porch part of said clamped composite video signal, a mixing circuit means which receives the reference voltage from said reference voltage source and detected voltage of said detection circuit means, and generates a signal of an intermediate voltage between said reference voltage and the detected back porch voltage, a separating circuit means for deriving synchronization signals by comparing the clamped composite video signal with said intermediate voltage signal, delay means, responsive to said synchronization signal, for generating said pulse signal to said detection means, a predetermined time period after said synchronization signals.

Claim 3

A synchronization signal separating circuit in accordance with claim 1, wherein said separating circuit means comprises a differential amplifier, which compares the clamped composite video signal with said intermediate voltage signal.

Claim 4

A synchronization signal separating circuit in accordance with claim 1, wherein said detection circuit means includes a switching circuit, responsive to said pulse signals, for passing said composite video signals only during said pulse signals, and a holding circuit means which is coupled to said switching means for holding the output thereof for generating the threshold voltage.

Claim 5

A synchronization signal separating circuit in accordance with claim 3, wherein said delay circuit means comprises a monostable multivibrator.

Claim 6

A synchronization signal separating circuit in accordance with claim 3, wherein said delay circuit means comprises at least one transistor with transmission delay caused by excess carrier in base region.

Claim 7

A synchronization signal separating circuit in accordance with claim 1, wherein said intermediate voltage generated by said mixing circuit is substantially in the middle of said reference and detected back porch voltages.

Claim 8

A synchronization signal separating circuit for deriving synchronization signals from a composite video signal, said circuit comprising: a reference voltage source for generating a predetermined reference voltage signal; clamp circuit means, receptive of said composite video signal, and said reference voltage signal, for clamping the sync chip level of the composite video signal to said reference voltage level; detection circuit means, responsive to said clamped composite video signal, for detecting the voltage of the back porch portion of said clamped composite video signal; mixing circuit means, responsive to said reference voltage signal and said detected back porch voltage, for generating a signal of an intermediate voltage between said reference voltage and said detected back porch voltage; separating circuit means, deriving synchronization signals by comparing the clamped composite video signal with said intermediate voltage signal; and delay circuit means for generating a signal pulse corresponding to the synchronization signal delayed by a specified delay time length; said detection circuit means including a switching circuit which passes the composite video signals only when the output signal of said delay circuit means is on, and a holding circuit means, coupled to said switching means, for holding the output thereof for generating the threshold voltage.

Claim 9

A synchronization signal separating circuit for deriving synchronization signals from a composite video signal, said circuit comprising: a reference voltage source for generating a predetermined reference voltage signal; clamp circuit means, receptive of said composite video signal, and said reference voltage signal, for clamping the sync chip level of the composite video signal to said reference voltage level; detection circuit means, responsive to said clamped composite video signal, for detecting the voltage of the back porch portion of said clamped composite video signal; mixing circuit means, responsive to said reference voltage signal and said detected back porch voltage, for generating a signal of an intermediate voltage between said reference voltage and said detected back porch voltage; separating circuit means, deriving synchronization signals by comparing the clamped composite video signal with said intermediate voltage signal; and delay circuit means for generating a signal pulse corresponding to the synchronization signal delayed by a specified delay time length; said detection circuit means including a switching circuit which passes the composite video signals only when the output signal of said delay circuit means is on, and a holding circuit means, coupled to said switching means, for holding the output thereof for generating the threshold voltage.

Claim 10

A synchronization signal separating circuit in accordance with claim 7, wherein; said delay circuit means comprises monostable multivibrator.

Claim 11

A synchronization signal separating circuit in accordance with claim 7, wherein; said delay circuit means comprises at least one transistor with transmission delay caused by excess carriers in base region.