Patent US4384345A successfully refreshed from Google Patents.
US4384345A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read-only memory device
Assignee: Fujitsu Ltd
•
Filing: 1981-05-08
•
Granted: 1983-05-17
•
Expires: 2001-05-08
Abstract
Abstract A read-only memory device comprising first and second memory cell areas is disclosed. In the first memory cell area, the presence or absence of a transistor represents the binary data "0" or "1", while, in the second memory cell area, the presence or absence of a connection for connecting a transistor to one of bit lines represents the binary data "0" or "1".
Inventors
- 👤 Koichi Mikome
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:50
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
228 words
A read-only memory device, for storing binary data having first and second level signals, comprising: first and second power supplies; a plurality of first word lines; a plurality of second word lines; a plurality of bit lines crossed with said first word lines and said second word lines and operatively connected to said first power supply; a first memory cell area comprising first memory cells at intersections between said first word lines and said bit lines, each first memory cell having a first transistor in dependence upon the first and second level signals of the binary data, each first memory cell present being operatively connected between a respective one of said first word lines and said bit line and to said second power supply, wherein the presence or absence of said first transistor represents a one of the first or second level signals of said binary data, respectively; and a second memory cell area comprising second memory cells at intersections between said second word lines and said bit lines, each second memory cell having a second transistor operatively connected to a respective one of said second word lines and to said second power supply, wherein the presence or absence of a connection for connecting said second transistor to one of said bit lines represents a one of the first or second level signals of the binary data, respectively.
Claim 2
Dependent Claim
228 words
A read-only memory device, for storing binary data having first and second level signals, comprising: first and second power supplies; a plurality of first word lines; a plurality of second word lines; a plurality of bit lines crossed with said first word lines and said second word lines and operatively connected to said first power supply; a first memory cell area comprising first memory cells at intersections between said first word lines and said bit lines, each first memory cell having a first transistor in dependence upon the first and second level signals of the binary data, each first memory cell present being operatively connected between a respective one of said first word lines and said bit line and to said second power supply, wherein the presence or absence of said first transistor represents a one of the first or second level signals of said binary data, respectively; and a second memory cell area comprising second memory cells at intersections between said second word lines and said bit lines, each second memory cell having a second transistor operatively connected to a respective one of said second word lines and to said second power supply, wherein the presence or absence of a connection for connecting said second transistor to one of said bit lines represents a one of the first or second level signals of the binary data, respectively.
Claim 3
Dependent Claim
35 words
A device as set forth in claim 1, wherein the presence and absence of each said first transistor are determined by the low and high levels of threshold voltages of each said first transistor, respectively.
Claim 4
Dependent Claim
44 words
A device as set forth in claim 1, wherein each said first transistor has a gate operatively connected to one of said first word lines, a drain connected to one of said bit lines and a source operatively connected to said second power supply.
Claim 5
Dependent Claim
66 words
A device as set forth in claim 1, wherein each said second transistor has a drain, a gate operatively connected to one of said second word lines and a source operatively connected to said second power supply, wherein the presence or absence of a connection for connecting the drain to one of said bit lines represents the first or second level signals of the binary data.
Claim 6
Dependent Claim
42 words
A device as set forth in claim 1, wherein a first information, which is basically not changed, is written into said first memory cell area, while a second information, which may be changed often, is written into said second memory cell area.
Claim 7
Dependent Claim
167 words
A read only memory device for storing predetermined binary data having first and second signals, comprising: first and second word lines; a bit line crossing said first and second word lines; a first memory cell area positioned at the intersection of said first word line and said bit line, including: a first transistor, operatively connected between said first word line and said bit line, having first a threshold value in dependence upon the first signal; and a second transistor, operatively connected between said word line and said bit line, having a second threshold value in dependence upon the second signal; and a second memory cell area positioned at the intersection of said second word line and said bit line, including: a third transistor operatively connected to said second word line and operatively connected to said bit line in dependence upon the first signal; and a fourth transistor operatively connected to said second word line and operatively connected to said bit line in dependence upon the second signal.
Claim 8
Dependent Claim
167 words
A read only memory device for storing predetermined binary data having first and second signals, comprising: first and second word lines; a bit line crossing said first and second word lines; a first memory cell area positioned at the intersection of said first word line and said bit line, including: a first transistor, operatively connected between said first word line and said bit line, having first a threshold value in dependence upon the first signal; and a second transistor, operatively connected between said word line and said bit line, having a second threshold value in dependence upon the second signal; and a second memory cell area positioned at the intersection of said second word line and said bit line, including: a third transistor operatively connected to said second word line and operatively connected to said bit line in dependence upon the first signal; and a fourth transistor operatively connected to said second word line and operatively connected to said bit line in dependence upon the second signal.
Claim 9
Dependent Claim
40 words
A read only memory device as set forth in claim 6, wherein said first and second transistors each have an oxide layer and said first and second threshold values being determined by the thickness of each of said oxide layers.
Claim 10
Dependent Claim
40 words
A read only memory device as set forth in claim 6, wherein said first and second transistors each have an oxide layer containing boron ions and said first and second threshold values being determined by the quantity of boron ions.
Claim 11
Dependent Claim
36 words
A read only memory device as set forth in claim 6, wherein said third and fourth transistors each have a contact window, operatively connecting said bit line, in dependence upon the first and second signals, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-16 | 1986-11-15 | 1987-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-16 | 1990-11-15 | 1991-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-16 | 1994-11-15 | 1995-05-17 | $7700.00 | Window Closed / Lapsed |