MOS Transistor circuit with a power-down function

Claim 2

A transistor circuit having a first input terminal, a second input terminal, and a circuit enable terminal, said circuit comprising: (a) a depletion-mode MOS transistor having a source, a drain, and a gate, the latter gate being connected to said first input terminal; (b) an enhancement-mode MOS transistor having a drain, a source, and a gate, the latter gate being connected to said second input terminal; and (c) an MOS transistor connected between said depletion-mode transistor and said enhancement-mode transistor for providing a power-down function, said power-down function transistor having a threshold voltage of approximately zero volts and also having a drain connected to said source of said depletion-mode MOS transistor, a source connected to said drain of said enhancement-mode transistor, and a gate connected to said circuit enable terminal.

Claim 3

The transistor circuit in claim 1, wherein said depletion-mode MOS transistor is a load transistor and said enhancement-mode MOS transistor is a drive transistor.

Claim 4

The transistor circuit in claim 1, wherein said threshold voltage of said power-down function transistor is between -0.5 volts to 0.2 volts.

Claim 5

The transistor circuit in claim 1, wherein a chip select signal is inputted to said circuit enable terminal for enabling or powering-down said circuit.

Claim 6

The transistor circuit in claim 1, wherein an output terminal is connected to said drain of said enhancement-mode MOS transistor.

Claim 7

The transistor circuit in claim 1 further including a power supply having at least two terminals wherein said drain of said depletion-mode MOS transistor is connected to a first terminal of said power supply and said source of said enhancement-mode MOS transistor is connected to a second terminal of said power supply.

Claim 8

The transistor circuit in claim 6 wherein said first terminal of said power supply is at a more positive potential than is said second terminal.

Claim 9

The transistor circuit in claim 1 wherein said first input terminal is connected to said source of said depletion-mode MOS transistor and wherein an output terminal is connected to said drain of said enhancement-mode transistor.

Claim 10

The transistor circuit of claim 1 wherein said first input terminal is an inverted signal input terminal and wherein a first output terminal is connected to said drain of said enhancement-mode transistor.

Claim 11

The transistor circuit in claim 9 further including a second output terminal connected to said drain of said power-down function MOS transistor.

Claim 12

A MOS transistor circuit having an input terminal, an inverted signal input terminal, and a first number of circuit enable terminals, said circuit comprising: (a) an enhancement-mode MOS transistor acting as a driver, said enhancement-mode transistor having a source, a drain, and a gate, the latter gate being connected to said input terminal; (b) a depletion-mode MOS transistor acting as a load, said depletion-mode transistor having a source, a drain, and a gate, said latter gate being connected to said inverted signal input terminal; and (c) a first number of MOS transistors providing a power-down function, each of said power-down function transistors having a threshold voltage of approximately zero volts and also having a source, a drain and a gate, said latter gate being connected to a different one of said first number of circuit enable terminals, said first number of power-down function transistors being connected between said depletion-mode MOS transistor and said enhancement-mode MOS transistor in a serial source-to-drain arrangement wherein the drain of one of said first number of power-down function transistors is connected to said source of said depletion-mode transistor and the source of another of said first number of power-down function transistors is connected to said drain of said enhancement-mode transistor.

Claim 13

A MOS transistor circuit having an input terminal, an inverted signal input terminal, and a first number of circuit enable terminals, said circuit comprising: (a) an enhancement-mode MOS transistor acting as a driver, said enhancement-mode transistor having a source, a drain, and a gate, the latter gate being connected to said input terminal; (b) a depletion-mode MOS transistor acting as a load, said depletion-mode transistor having a source, a drain, and a gate, said latter gate being connected to said inverted signal input terminal; and (c) a first number of MOS transistors providing a power-down function, each of said power-down function transistors having a threshold voltage of approximately zero volts and also having a source, a drain and a gate, said latter gate being connected to a different one of said first number of circuit enable terminals, said first number of power-down function transistors being connected between said depletion-mode MOS transistor and said enhancement-mode MOS transistor in a serial source-to-drain arrangement wherein the drain of one of said first number of power-down function transistors is connected to said source of said depletion-mode transistor and the source of another of said first number of power-down function transistors is connected to said drain of said enhancement-mode transistor.