← Back to Patent Explorer
US4382285A Expired / Lapsed US ⏱️ 0.0 years remaining

Filter for binary data with integral output amplitude multiplier

Assignee: Motorola Solutions Inc
•
Filing: 1980-12-30
•
Granted: 1983-05-03
•
Expires: 2000-12-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A filter for digital data comprises a plurality of cascaded latches clocked to form a plurality of flip-flops. A series-parallel network of resistors connected to outputs of the latches renders the circuit a filter that can be constructed with a limited resistance ratio. A plurality of switches connected to outputs of the flip-flops and operated by those outputs effects both filtering and multiplication by a voltage that is switched into the resistive network by the switches.

Inventors

  • 👤 Terence E. Sumner
  • 👤 James Ward
  • 👤 Alan L. Wilson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 12:11
CPC Classifications
H; H03; H03H; H03H15/00

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 133 words
A multiplying filter for digital data comprising: a plurality of cascaded clocked latches, alternate latches of the plurality clocked oppositely so that pairs of adjacent latches form cascaded flip-flops; a plurality of voltage-operated switches, one of each of the switches connected to an output of one of the latches; a first voltage source connected to each of the plurality of switches and connected through upon a first signal from a latch; a second voltage source connected to each of the plurality of switches and connected through upon a second signal from a latch; a network of resistors, one of each of the resistors connected through one of the plurality of switches to one of the first and second voltage sources, the network having a central point that is an output of the filter.
Claim 2
Dependent Claim 133 words
A multiplying filter for digital data comprising: a plurality of cascaded clocked latches, alternate latches of the plurality clocked oppositely so that pairs of adjacent latches form cascaded flip-flops; a plurality of voltage-operated switches, one of each of the switches connected to an output of one of the latches; a first voltage source connected to each of the plurality of switches and connected through upon a first signal from a latch; a second voltage source connected to each of the plurality of switches and connected through upon a second signal from a latch; a network of resistors, one of each of the resistors connected through one of the plurality of switches to one of the first and second voltage sources, the network having a central point that is an output of the filter.
Claim 3
Dependent Claim 36 words
The filter of claim 1 wherein the network of resistors comprises resistors of which the ratio of resistance of the largest resistor to the resistance of the smallest resistor is less than or equal to 2.5.
Claim 4
Dependent Claim 12 words
The filter of claim 1 wherein the voltage-operated switches are transmission gates.
Claim 5
Dependent Claim 23 words
The filter of claim 1 wherein the first voltage source is a time-varying voltage source and the second voltage source is zero volts.

References Cited (Backward Citations)

US3543009A Cited
US3633170A Cited
US3825831A Cited
US3753115A Cited
USRE28638E Cited
US3694752A Cited
US3801934A Cited
US4044306A Cited
US4149259A Cited
US4012628A Cited
US4151517A Cited
US4233684A Cited
US4323864A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-05-02 1986-11-01 1987-05-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-05-02 1990-11-01 1991-05-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-05-02 1994-11-01 1995-05-03 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag