US3694752A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed transmission receiver utilizing fine receiver timing and carrier phase recovery
Assignee: Boeing North American Inc
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Filing: 1971-03-18
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Granted: 1972-09-26
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Expires: 1991-03-18
Abstract
Abstract The invention is directed to an improvement in a digital data receiver of the type which utilizes an adaptive equalizer having a plurality of adjustable attenuators to remove distortion in received signals. The improvement comprises a system which utilizes the signals available at the equalizer adjustable attenuators to achieve accurate and stable carrier phase and timing control signals.
Inventors
- 👤 Earl D Gibson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:38
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/0058; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03038; H04L25/0305; H04L27/00; H04L27/02; H04L27/06; H04L27/066
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
366 words
In combination with a high speed digital data receiver having a transversal equalizer with multiple adjustable attenuators, the improvement comprising: a first comparator connected to the output of at least two adjustable attenuators of said equalizer, said first comparator providing an output signal corresponding to the sign of the difference between the gains at said two adjustable attenuators of said equalizer, said first comparator providing an output signal corresponding to the sign of the difference between the gains at said two adjustable attenuators; a second comparator connected to the output of at least two other of the adjustable attenuators of said equalizer, said second comparator providing an output signal corresponding to the sign of the difference between the gains at said other two adjustable attenuators; a clock means for providing a train of clock pulses; a first and a second ADD/DELETE means receiving as an input said train of clock pulses; first and second gate means connected to receive the output signal from said first and said second comparators, respectively; a fixed rate alternating switch means for connecting the output of said second gate means alternately to the input of said first and said second ADD/DELETE means; a first switch means for connecting the input of said first ADD/DELETE means in one position to the output of said first gate means and in the other position to said fixed rate alternating switch means; first and second frequency divider means connected to receive the output from said first and said second ADD/DELETE means, respectively, the output of said first frequency divider means being a train of pulses that are proportional to the output carrier with the output of said second frequency divider being a train of pulses proportional to the output baud timing; and two feedback means for connecting selected outputs from said second frequency divider means back to said first and said second gate means so as to control the time intervals at which said first and said second ADD/DELETE means add or delete pulses to the pulse trains entering said first and said second frequency dividers, thereby controlling the time intervals between consecutive incremental adjustments of the output carrier phase and the output baud timing.
Claim 2
Dependent Claim
366 words
In combination with a high speed digital data receiver having a transversal equalizer with multiple adjustable attenuators, the improvement comprising: a first comparator connected to the output of at least two adjustable attenuators of said equalizer, said first comparator providing an output signal corresponding to the sign of the difference between the gains at said two adjustable attenuators of said equalizer, said first comparator providing an output signal corresponding to the sign of the difference between the gains at said two adjustable attenuators; a second comparator connected to the output of at least two other of the adjustable attenuators of said equalizer, said second comparator providing an output signal corresponding to the sign of the difference between the gains at said other two adjustable attenuators; a clock means for providing a train of clock pulses; a first and a second ADD/DELETE means receiving as an input said train of clock pulses; first and second gate means connected to receive the output signal from said first and said second comparators, respectively; a fixed rate alternating switch means for connecting the output of said second gate means alternately to the input of said first and said second ADD/DELETE means; a first switch means for connecting the input of said first ADD/DELETE means in one position to the output of said first gate means and in the other position to said fixed rate alternating switch means; first and second frequency divider means connected to receive the output from said first and said second ADD/DELETE means, respectively, the output of said first frequency divider means being a train of pulses that are proportional to the output carrier with the output of said second frequency divider being a train of pulses proportional to the output baud timing; and two feedback means for connecting selected outputs from said second frequency divider means back to said first and said second gate means so as to control the time intervals at which said first and said second ADD/DELETE means add or delete pulses to the pulse trains entering said first and said second frequency dividers, thereby controlling the time intervals between consecutive incremental adjustments of the output carrier phase and the output baud timing.
Claim 3
Dependent Claim
348 words
In combination with an adjustable transversal equalizer having a plural tapped delay line, with adjustable attenuators connected to at least each delay line with one main tap for a major signal component and a summation circuit for combining the attenuated outputs of the adjustable attenuators into a single coordinated signal, a carrier and timing recovery system comprising in combination: a first comparing means for taking the difference between first adjustable attenuators outputs located on either side of said main signal tap attenuator and for providing a difference signal proportional to said difference; a second comparing means for taking the difference between adjustable attenuator outputs located on either side of said first adjustable attenuators and for providing a difference signal proportional to said difference; a first and second gate means for receiving the difference signal from said first and second comparing means, respectively, and for gating the received signals to individual output terminals upon receipt of respective control signals; a first and a second pulse generating means for generating trains of pulses, said generating means incrementally advancing or retarding the phase of said trains of pulses, the choice between advancing or retarding being controlled by the sign of said difference signal from said first or said second comparing means, respectively, the timing of each advance/retardation being controlled by said first and said second gate means, respectively, the output pulses from said first pulse generating means being the system''s output carrier pulses and the output pulses from said second pulse generating means being the system''s output timing pulses, said system output timing pulses being fed back through additional frequency division to said first and said second gate means as said control signals; alternating switch means for alternately connecting the output terminal of said second gate means to the inputs of said first and said second pulse generating means; and switch means interposed at the input of said first pulse generating means for connecting said input in one position to the output terminal of said first gating means and in the other position to the output of said alternating switch means.
Claim 4
Dependent Claim
348 words
In combination with an adjustable transversal equalizer having a plural tapped delay line, with adjustable attenuators connected to at least each delay line with one main tap for a major signal component and a summation circuit for combining the attenuated outputs of the adjustable attenuators into a single coordinated signal, a carrier and timing recovery system comprising in combination: a first comparing means for taking the difference between first adjustable attenuators outputs located on either side of said main signal tap attenuator and for providing a difference signal proportional to said difference; a second comparing means for taking the difference between adjustable attenuator outputs located on either side of said first adjustable attenuators and for providing a difference signal proportional to said difference; a first and second gate means for receiving the difference signal from said first and second comparing means, respectively, and for gating the received signals to individual output terminals upon receipt of respective control signals; a first and a second pulse generating means for generating trains of pulses, said generating means incrementally advancing or retarding the phase of said trains of pulses, the choice between advancing or retarding being controlled by the sign of said difference signal from said first or said second comparing means, respectively, the timing of each advance/retardation being controlled by said first and said second gate means, respectively, the output pulses from said first pulse generating means being the system''s output carrier pulses and the output pulses from said second pulse generating means being the system''s output timing pulses, said system output timing pulses being fed back through additional frequency division to said first and said second gate means as said control signals; alternating switch means for alternately connecting the output terminal of said second gate means to the inputs of said first and said second pulse generating means; and switch means interposed at the input of said first pulse generating means for connecting said input in one position to the output terminal of said first gating means and in the other position to the output of said alternating switch means.
Claim 5
Dependent Claim
120 words
The invention according to claim 2 wherein said second pulse generating means is comprised of: a clock means for generating a train of clock pulses at a frequency greater than the desired system baud frequency; means responsive to the output signal of said second gating means for adding or deleting a pulse from said clock pulse train according to the sign of said output signal; frequency down counter means for dividing the pulse train from said ADD/DELETE means down to at least the desired baud frequency to provide gate timing control pulse trains; and first and second switch means for coNnecting the provided gate timing control pulse trains to the control terminal of said first and second gate means, respectively.
Claim 6
Dependent Claim
94 words
The invention according to claim 2 wherein said first pulse generating means is comprised of: a clock means for generating a train of clock pulses at a frequency greater than the desired system''s baud frequency; means responsive to the output signal of said first gating means for adding or deleting a pulse from said clock pulse train according to the sign of said output signal; and frequency down counter means for dividing the pulse train from said ADD/DELETE means down to at least the desired baud frequency to provide the system''s output carrier pulses.
Claim 7
Dependent Claim
242 words
In combination with a high speed digital data receiver having a transversal equalizer with multiple tap gains and adjustable attenuators connected to each of the tap gains, the improvement comprising: a first comparator connected to the output of at least two adjustable attenuators of said equalizer, said first comparator providing an output signal which is a function of the difference between the outputs of said two adjustable attenuators; a second comparator connected to at least two other of the outputs of said adjustable attenuators, said second comparator providing an output signal corresponding to the sign of the difference between the outputs of the two other adjustable attenuators; means for providing a periodic pulse train signal; a first modulating means responsive to the signal from said first comparator for modulating said periodic pulse train means; a second modulating means responsive to the signal from said second comparator for modulating the signal from said periodic pulse train means; first and second frequency divider means connected to receive the output from said first and said second modulating means, respectively; switch means interposed between the output of said first and second modulating means for controllably connecting the output of said first and second modulating means to said first and said second comparator; and feedback means for receiving a signal from said second frequency divider means and feeding said signal to said switch means to control the output signals to said first and said second modulating means.
Claim 8
Dependent Claim
242 words
In combination with a high speed digital data receiver having a transversal equalizer with multiple tap gains and adjustable attenuators connected to each of the tap gains, the improvement comprising: a first comparator connected to the output of at least two adjustable attenuators of said equalizer, said first comparator providing an output signal which is a function of the difference between the outputs of said two adjustable attenuators; a second comparator connected to at least two other of the outputs of said adjustable attenuators, said second comparator providing an output signal corresponding to the sign of the difference between the outputs of the two other adjustable attenuators; means for providing a periodic pulse train signal; a first modulating means responsive to the signal from said first comparator for modulating said periodic pulse train means; a second modulating means responsive to the signal from said second comparator for modulating the signal from said periodic pulse train means; first and second frequency divider means connected to receive the output from said first and said second modulating means, respectively; switch means interposed between the output of said first and second modulating means for controllably connecting the output of said first and second modulating means to said first and said second comparator; and feedback means for receiving a signal from said second frequency divider means and feeding said signal to said switch means to control the output signals to said first and said second modulating means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-26 | 1976-03-27 | 1976-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-26 | 1980-03-27 | 1980-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-26 | 1984-03-27 | 1984-09-26 | $7700.00 | Window Closed / Lapsed |