Patent US4380863A successfully refreshed from Google Patents.
US4380863A
Expired / Lapsed
US
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Method of making double level polysilicon series transistor devices
Assignee: Texas Instruments Inc
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Filing: 1982-01-26
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Granted: 1983-04-26
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Expires: 2002-01-26
Abstract
Abstract A plurality of MOS transistors are formed as an integrated semiconductor device, adjacent transistors sharing a common source/drain region which is created by the edges of inverted regions beneath the gates of the transistors. These gates are first and second level polysilicon, with the second partly overlapping the first. On the opposite ends, the source and drain regions are formed by diffusion using the oxide under the first and second level poly as the diffusion mask.
Inventors
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D30/00; H10D30/60; H10D30/611; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D84/83125; H10D84/83138
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
89 words
A method of making a pair of adjacent semiconductor devices comprising the steps of applying a first layer on a face of a semiconductor body then patterning it to define an electrode of one of the devices, applying a second layer on said face and patterning it to define an electrode of the other of the semiconductor devices, the second layer partially overlapping the first layer, then introducing impurity material into the face using the first and second layers as a mask to create regions of the semiconductor devices.
Claim 2
Independent Claim
89 words
A method of making a pair of adjacent semiconductor devices comprising the steps of applying a first layer on a face of a semiconductor body then patterning it to define an electrode of one of the devices, applying a second layer on said face and patterning it to define an electrode of the other of the semiconductor devices, the second layer partially overlapping the first layer, then introducing impurity material into the face using the first and second layers as a mask to create regions of the semiconductor devices.
Claim 3
Dependent Claim
32 words
A method according to claim 1 wherein the semiconductor devices are insulated gate field effect transistors and each of the first and second layers include an insulating coating and a conductive layer.
Claim 4
Dependent Claim
26 words
A method according to claim 2 wherein the conductive layer of the first and second layers is polycrystalline silicon, and the insulating coating is silicon oxide.
Claim 5
Dependent Claim
27 words
A method according to claim 3 wherein an insulating coating is applied between the first layer and the second layer at the area of said partial overlapping.
Claim 6
Dependent Claim
40 words
A method according to claim 4 wherein the step of introducing impurity material includes diffusing to create heavily-doped regions in the face, the silicon oxide beneath the polycrystalline silicon of the first and second layers acting as a diffusion mask.
Claim 7
Independent Claim
100 words
A method of making a plurality of adjacent semiconductor devices comprising the steps of applying a first layer on a face of a semiconductor body then patterning it to define an electrode at least of one of the devices, applying a second layer on said face and patterning it to define an electrode of at least one other of the devices, the second layer partially overlapping the first layer and being insulated therefrom, then introducing impurity material into the face using the first and second layers as a mask to create a region of at least two of the devices.
Claim 8
Independent Claim
100 words
A method of making a plurality of adjacent semiconductor devices comprising the steps of applying a first layer on a face of a semiconductor body then patterning it to define an electrode at least of one of the devices, applying a second layer on said face and patterning it to define an electrode of at least one other of the devices, the second layer partially overlapping the first layer and being insulated therefrom, then introducing impurity material into the face using the first and second layers as a mask to create a region of at least two of the devices.
Claim 9
Dependent Claim
41 words
A method according to claim 6 wherein the semiconductor devices include at least three insulated gate field effect transistors and each of the first and second layers include a conductive layer forming the gate of at least one of the transistors.
Claim 10
Dependent Claim
39 words
A method according to claim 7 wherein the first layer forms the gates of one of said transistors and the second layer forms the gate of two of the transistors, said one being between such two of the transistors.
Claim 11
Dependent Claim
36 words
A method according to claim 8 wherein the step of introducing impurity material includes diffusing to create heavily-doped regions in the face, and silicon oxide beneath the first and second layers acts as a diffusion mask.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-25 | 1986-10-25 | 1987-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-25 | 1990-10-25 | 1991-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-25 | 1994-10-25 | 1995-04-26 | $7700.00 | Window Closed / Lapsed |