Patent US4380082A successfully refreshed from Google Patents.
US4380082A
Expired / Lapsed
US
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Digital signal receiver with FM interference elimination capability
Assignee: NEC Corp
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Filing: 1981-04-24
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Granted: 1983-04-12
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Expires: 2001-04-24
Abstract
Abstract The invention eliminates an FM interference from a digital signal when the interference occurs because the FM and digital signals are transmitted over adjacent routes and sharing a common frequency band. An error detector finds a difference between a detected baseband digital signal and an assumed transmission code, which is taken from the baseband signal. The detector produces a first error signal responsive thereto. A phase synchronizing circuit produces an output signal synchronized with the first error signal. A coefficient circuit multiplies the output of the synchronizing circuit by a complex coefficient which is then subtracted from the baseband signal. A second error detector produces a second error signal responsive to the difference between the output of the subtractor and a discriminated transmission code. Responsive thereto to a control circuit varies the complex coefficient to produce an output which is the original baseband signal, free of the FM interference.
Inventors
- 👤 Junji Namiki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 04:28
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/06; H04B1/10; H04L; H04L25/00; H04L25/02; H04L25/08
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
198 words
A digital signal receiver for eliminating FM interference in a received digital baseband signal, which appears on at least one adjacent route sharing the same frequency band, said receiver comprising first error detector means responsive to the received baseband signal for giving an error signal representing a difference between said baseband signal and a discriminated transmission code; phase synchronizing means responsive to said first error detector means for producing an output signal which is synchronized with a complex value output of the first error detector means; coefficient circuit means responsive to said phase synchronizing means for multiplying the output of the synchronizing means by a complex coefficient; subtractor means responsive to said coefficient circuit means for subtracting the output of the coefficient circuit from said baseband signal; second error detector means responsive to said subtractor means for giving a second error signal representing the difference between the output of said subtractor means and a transmission code discriminated from the output of the subtractor; and a control circuit means for varying the complex coefficient of the coefficient circuit means based on the correlation between the output of the second error detector means and the output of the synchronizing means.
Claim 2
Dependent Claim
198 words
A digital signal receiver for eliminating FM interference in a received digital baseband signal, which appears on at least one adjacent route sharing the same frequency band, said receiver comprising first error detector means responsive to the received baseband signal for giving an error signal representing a difference between said baseband signal and a discriminated transmission code; phase synchronizing means responsive to said first error detector means for producing an output signal which is synchronized with a complex value output of the first error detector means; coefficient circuit means responsive to said phase synchronizing means for multiplying the output of the synchronizing means by a complex coefficient; subtractor means responsive to said coefficient circuit means for subtracting the output of the coefficient circuit from said baseband signal; second error detector means responsive to said subtractor means for giving a second error signal representing the difference between the output of said subtractor means and a transmission code discriminated from the output of the subtractor; and a control circuit means for varying the complex coefficient of the coefficient circuit means based on the correlation between the output of the second error detector means and the output of the synchronizing means.
Claim 3
Dependent Claim
90 words
A digital signal receiver comprising error detector means for generating an error signal based upon detected differences between discriminated transmission codes and received digital baseband signals, synchronizing means responsive to said error signal for synchronizing said error signal with a complex value correcting signal, means for multiplying the output signal of said synchronizing means with a predetermined coefficient signal, subtracting means for extracting said multiplied correcting signal from said digital signal, and control means responsive to said subtracting means for adjusting said coefficient to produce an interference free digital signal.
Claim 4
Dependent Claim
90 words
A digital signal receiver comprising error detector means for generating an error signal based upon detected differences between discriminated transmission codes and received digital baseband signals, synchronizing means responsive to said error signal for synchronizing said error signal with a complex value correcting signal, means for multiplying the output signal of said synchronizing means with a predetermined coefficient signal, subtracting means for extracting said multiplied correcting signal from said digital signal, and control means responsive to said subtracting means for adjusting said coefficient to produce an interference free digital signal.
Claim 5
Dependent Claim
60 words
The receiver of claim 2 wherein said error detector means comprises a discriminator means and a subtractor means, and means for applying said received digital signal both directly to said subtractor means and through said discriminator means to said subtractor means, the output of said subtractor representing the difference between said directly applied signal and the output of said discriminator.
Claim 6
Dependent Claim
49 words
The receiver of claim 2 wherein said synchronizing means comprises a voltage controlled oscillator, and phase difference detection means for controlling said voltage controlled oscillator responsive to a combination of said error signal and an output of said voltage controlled oscillator fed back to said phase difference detection means.
Claim 7
Dependent Claim
32 words
The receiver of claim 4 and means responsive to said phase difference responsive means for extracting a part of said combination signal before it is applied to said voltage controlled correcting means.
Claim 8
Dependent Claim
31 words
The receiver of either the claims 4 or 5 and means for applying the output of said voltage controlled oscillator to said coefficient multiplier means, thereby producing said multiplied correcting signal.
Claim 9
Dependent Claim
42 words
The receiver of claim 6 and second discriminator means, second subtractor means, said control means comprising means for applying the output of said subtracting means directly to said second subtractor means and through said second discriminator means to said second subtractor means.
Claim 10
Dependent Claim
37 words
The receiver of claim 7 and means for integrating the output of said second subtractor means and means responsive to an inversion of the output of said second subtractor means for making said adjustment of said coefficient.
Claim 11
Dependent Claim
77 words
A process for eliminating an FM interference in a received digital baseband signal, said process comprising the steps of: (a) detecting a difference between the received signal and an anticipated signal; (b) synchronizing the detected difference with a complex output signal; (c) multiplying the synchronized signal by a coefficient signal; (d) combining the multiplied signal with the received signal; (e) sampling said combined signal; and (f) adjusting said coefficient as a function of said sampled combined signal.
Claim 12
Dependent Claim
77 words
A process for eliminating an FM interference in a received digital baseband signal, said process comprising the steps of: (a) detecting a difference between the received signal and an anticipated signal; (b) synchronizing the detected difference with a complex output signal; (c) multiplying the synchronized signal by a coefficient signal; (d) combining the multiplied signal with the received signal; (e) sampling said combined signal; and (f) adjusting said coefficient as a function of said sampled combined signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-11 | 1986-10-11 | 1987-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-11 | 1990-10-11 | 1991-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-11 | 1994-10-11 | 1995-04-12 | $7700.00 | Window Closed / Lapsed |