US3613077A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error correction in sampled-data circuits
Assignee: Motorola Solutions Inc
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Filing: 1969-08-25
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Granted: 1971-10-12
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Expires: 1989-08-25
Abstract
Abstract Error correction in modems and similar sampled-data circuits that have outputs representable as outputs of a linear circuit with integer-valued impulse response when the integer-valued input sequence is subject to predetermined constraints. Integervalued tentative decisions and reliability information are formed and stored. A correction is made upon detection, on the basis of the constraints, of an error in the tentative decisions. Shown also are: an inverse linear circuit for detecting decision errors according to whether its outputs satisfy the constraints, with means to combat propagation of the error in the inverse circuit; reliability information in the form of magnitude and sign of apparent errors, especially storing only the extreme values of apparent errors in the sequence under review; constraints in form of predetermined finite range of integers and detection with an inverse circuit on basis of values falling outside of the finite range, also combating propagation by replacement of erroneous value with closest substitute satisfying the constraints; and impulse responses of the form 1 + OR - Dn, where n integer, and division of tentative decisions and memory into related groups.
Inventors
- 👤 George David Forney Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:33
CPC Classifications
H; H04; H04L; H04L1/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
222 words
In a modem or similar device in which there are time-discrete data samples representable as the sum of a desired output plus noise, said desired output being representable as the output of a linear sampled-data circuit with integer-valued impulse response when the input is a sequence of integer-valued input samples subject to predetermined constraints, said noise being likely to be small compared to a unit interval, an error corrector comprising: a tentative decision circuit responsive to said data samples and having as outputs integer-valued tentative decision signals and signals indicating the reliability of said decisions; memory means for storage of both a predetermined number of successive tentative decision signals, and of reliability information derived from said reliability-indicating signals, said reliability information comprising at least an indication of the location of the least reliable of said tentative decision signals; a detection circuit responsive to said tentative decision signals for detecting the occurrence of errors in said tentative decision signals on the basis of said constraints, said detection circuit providing output signals indicative of the presence or absence of tentative decision errors; and correction logic responsive to said detection circuit output signals and to said stored reliability information for determining the probable location, magnitude, and polarity of said tentative decision errors, with means for implementing correction of said errors in said tentative decision signals.
Claim 2
Dependent Claim
222 words
In a modem or similar device in which there are time-discrete data samples representable as the sum of a desired output plus noise, said desired output being representable as the output of a linear sampled-data circuit with integer-valued impulse response when the input is a sequence of integer-valued input samples subject to predetermined constraints, said noise being likely to be small compared to a unit interval, an error corrector comprising: a tentative decision circuit responsive to said data samples and having as outputs integer-valued tentative decision signals and signals indicating the reliability of said decisions; memory means for storage of both a predetermined number of successive tentative decision signals, and of reliability information derived from said reliability-indicating signals, said reliability information comprising at least an indication of the location of the least reliable of said tentative decision signals; a detection circuit responsive to said tentative decision signals for detecting the occurrence of errors in said tentative decision signals on the basis of said constraints, said detection circuit providing output signals indicative of the presence or absence of tentative decision errors; and correction logic responsive to said detection circuit output signals and to said stored reliability information for determining the probable location, magnitude, and polarity of said tentative decision errors, with means for implementing correction of said errors in said tentative decision signals.
Claim 3
Dependent Claim
76 words
The device of claim 1 wherein said detection circuit comprises: a linear circuit which is the inverse of said first-mentioned linear circuit, said inverse circuit connected to receive as inputs said tentative decision signals; detection logic responsive to the outputs of said inverse circuit to determine the presence or absence of decision errors according to whether the outputs satisfy said constraints; and means to prevent the propagation of a detected decision error in said inverse circuit.
Claim 4
Dependent Claim
53 words
The device of claim 2 wherein said input constraints are that input values are restricted to a finite predetermined range of integers and in which said detection circuit determines the presence or absence of decision errors according to whether the outputs of said inverse linear circuit fall inside or outside said finite range.
Claim 5
Dependent Claim
55 words
The dEvice of claim 3 wherein said means to prevent propagation comprises circuitry connected to cause replacement of any output of said inverse circuit for which input finite range constraints are not satisfied with a substituted output, said substituted output having the closest integer value to said output which satisfies said input finite range constraints.
Claim 6
Dependent Claim
42 words
The device of claim 1 wherein said reliability-indicating signals include the magnitudes of the apparent errors in said data samples, said apparent errors being equal to the differences between said data samples and the levels associated with the corresponding tentative decision signals.
Claim 7
Dependent Claim
37 words
The device of claim 5 wherein said reliability-indicating signals include also the signs of said apparent errors and said stored reliability information comprises at least signals indicating the locations of the largest positive and negative apparent errors.
Claim 8
Dependent Claim
29 words
The device of claim 6 wherein said stored reliability information comprises all of said apparent errors associated with all of said tentative decision signals stored in said memory means.
Claim 9
Dependent Claim
22 words
The device of claim 1 wherein said input constraints are that input values are restricted to a predetermined finite range of intergers.
Claim 10
Dependent Claim
28 words
The device of claim 1 wherein said integer-valued impulse response is defined by a transfer function of the form 1 + or -Dn, where n is an integer.
Claim 11
Dependent Claim
60 words
The device of claim 1 wherein said tentative decision signals comprise a plurality of output sets, each set comprising signals which are affected by errors only in prior signals of the same set, and wherein said memory means comprises a like plurality of separate portions for the separate storage of reliability information corresponding to each of said plurality of sets.
Claim 12
Dependent Claim
19 words
The device of claim 10 wherein said plurality of output sets and said plurality of memory portions is two.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-11 | 1975-04-12 | 1975-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-11 | 1979-04-12 | 1979-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-11 | 1983-04-12 | 1983-10-12 | $7700.00 | Window Closed / Lapsed |