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US4380068A
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Test unit for a high-rate multitrack digital recorder
Assignee: Thales SA
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Filing: 1981-01-19
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Granted: 1983-04-12
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Expires: 2001-01-19
Abstract
Abstract The unit for testing a plurality of tracks of a high-speed recorder in parallel comprises an emission subassembly for the transmission of data to the recorder to be tested and a test subassembly. The emission subassembly mainly comprises a generator for producing a pseudo-random or ramp-function sequence of binary numbers consisting of a plurality of binary elements in parallel. The test subassembly comprises a data storage device for storing the data reproduced by the tested recorder, a second generator programmed in the same manner as the first, a device for comparing the reproduced sequence with the emitted sequence and an error analysis device which delivers a measurement of the error rate and serves to locate the detected errors.
Inventors
- 👤 Tristan de Couasnon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:37
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1816; G11B20/182
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
226 words
A test unit for a high-rate multitrack digital recorder, said unit having a multiple input and output and comprising: a first generator for producing a sequence of binary numbers and connected to said multiple output for transmitting data to the recorder to be tested; a data storage means connected to said multiple input of said test unit for storing the data reproduced by the tested recorder; a second generator for producing the same sequence of binary numbers; means for comparing the reproduced sequence with the emitted sequence, said comparing means being connected to the output of the storage means to the output of the second generator; an error analysis means connected to the output of the comparison means for counting the errors introduced by the recorder to be tested and detected by the comparing means; and said error analysis means including a first counter for counting detected errors and means for locating detected errors, said error locating means including a second counter for counting reproduced binary numbers and delivering at each instant the address of the binary number analyzed in the sequence and a storage memory means connected to said comparing means and to said second counter and having a control input for causing storage of addresses of binary numbers in which errors are detected and the position of the detected errors in each erroneous number.
Claim 2
Dependent Claim
226 words
A test unit for a high-rate multitrack digital recorder, said unit having a multiple input and output and comprising: a first generator for producing a sequence of binary numbers and connected to said multiple output for transmitting data to the recorder to be tested; a data storage means connected to said multiple input of said test unit for storing the data reproduced by the tested recorder; a second generator for producing the same sequence of binary numbers; means for comparing the reproduced sequence with the emitted sequence, said comparing means being connected to the output of the storage means to the output of the second generator; an error analysis means connected to the output of the comparison means for counting the errors introduced by the recorder to be tested and detected by the comparing means; and said error analysis means including a first counter for counting detected errors and means for locating detected errors, said error locating means including a second counter for counting reproduced binary numbers and delivering at each instant the address of the binary number analyzed in the sequence and a storage memory means connected to said comparing means and to said second counter and having a control input for causing storage of addresses of binary numbers in which errors are detected and the position of the detected errors in each erroneous number.
Claim 3
Dependent Claim
204 words
A test unit for a high-rate multitrack digital recorder, said unit having a multiple input and output and comprising: a first generator for producing a sequence of binary numbers and connected to said multiple output for transmitting data to the recorder to be tested; a data storage means connected to said multiple input of said test unit for storing the data reproduced by the tested recorder; a second generator for producing the same sequence of binary numbers; means for comparing the reproduced sequence with the emitted sequence, said comparing means being connected to the output of the storage means and to the output of the second generator; and an error analysis means connected to the output of the comparing means for counting the errors introduced by the recorder to be tested and detected by the comparing means; said storage means comprising a stack of memory registers for storing a plurality of successive binary numbers of the reproduced sequence, and a decoding logic means connected to the outputs of the memory registers, a synchronization signal being delivered by one output of said decoding means to the second generator and the comparing means for a predetermined succession of numbers identified as the beginning of a sequence.
Claim 4
Dependent Claim
204 words
A test unit for a high-rate multitrack digital recorder, said unit having a multiple input and output and comprising: a first generator for producing a sequence of binary numbers and connected to said multiple output for transmitting data to the recorder to be tested; a data storage means connected to said multiple input of said test unit for storing the data reproduced by the tested recorder; a second generator for producing the same sequence of binary numbers; means for comparing the reproduced sequence with the emitted sequence, said comparing means being connected to the output of the storage means and to the output of the second generator; and an error analysis means connected to the output of the comparing means for counting the errors introduced by the recorder to be tested and detected by the comparing means; said storage means comprising a stack of memory registers for storing a plurality of successive binary numbers of the reproduced sequence, and a decoding logic means connected to the outputs of the memory registers, a synchronization signal being delivered by one output of said decoding means to the second generator and the comparing means for a predetermined succession of numbers identified as the beginning of a sequence.
Claim 5
Dependent Claim
29 words
A test unit according to claim 1 or claim 2, wherein the first and second sequence generators each have a programmed memory with a pseudo-random series of binary numbers.
Claim 6
Dependent Claim
55 words
A test unit according to claim 1 or claim 2, wherein the first and second sequence generators each have a programmed memory with a pseudo-random series and a continuous series of binary numbers, the test unit being provided with a control input connected to the two generators aforesaid for selecting either of these two series.
Claim 7
Dependent Claim
57 words
A test unit according to claim 1, wherein the two generators have two operating modes, namely a sequential mode in which the binary numbers of the sequence are emitted successively and a repetitive mode in which the binary numbers of the sequence are emitted several times in succession, the test unit being provided with a mode-control input.
Claim 8
Dependent Claim
25 words
A test unit according to claim 1, wherein said unit further comprises a display device coupled to the detected-error counter and to the storage memory.
Claim 9
Dependent Claim
46 words
A test unit according to claim 1, wherein said unit has a multiple analysis output connected on the one hand to the error counter and on the other hand to the storage memory, said multiple output being intended to be connected to a logical state analyzer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-11 | 1986-10-11 | 1987-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-11 | 1990-10-11 | 1991-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-11 | 1994-10-11 | 1995-04-12 | $7700.00 | Window Closed / Lapsed |