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US4380022A
Expired / Lapsed
US
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Monolithic fully integrated class B push-pull microwave GaAs MESFET with differential inputs and outputs with reduced Miller effect
Assignee: United States Department of the Navy
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Filing: 1980-12-09
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Granted: 1983-04-12
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Expires: 2000-12-09
Abstract
Abstract A class B microwave, push-pull, balanced amplifier and an amplifying element for use therein is disclosed. A field-effect transistor having at least two gates, two drains and a common source has, inter alia, a center-tapped output transformer connected across the drains. A branch including a DC voltage source connects the center-tap of the transformer and the common source of the field effect transistor. Parasitic loss mechanisms associated with the source contacts and leads are eliminated because the current in the branch connecting the source to the transformer is not at the signal frequency. The FET can comprise a semiconductor body having alternating drain and source electrodes with gate electrodes therebetween. Source electrodes are connected in common. Alternate drain electrodes are connected to one output terminal; the remaining drain electrodes are connected to the other output terminal. The two gate electrodes lying between any two consecutive drain electrodes are respectively connected to opposite input terminals.
Inventors
- 👤 Max N. Yoder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:09
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H03; H03F; H03F3/00; H03F3/26; H03F3/265; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/02; H10D84/05
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
315 words
An improved field effect transistor device of the type having a body of semiconductor material, and a plurality of drains, gates and sources operatively disposed on the body of semiconductor material, said field effect transistor device being connected in a differential input and output configuration including a positive gate bus, a negative gate bus, a positive drain bus, a negative drain bus, and a common source bus, wherein the improvement for a single one of a plurality of alternate parallel connected operating units of said field effect transistor device comprises: a common source operatively connected to the common source bus; first and second drains juxtaposed on opposite sides of said common source, said first drain being operatively connected to the negative drain bus, and said second drain being operatively connected to the positive drain bus; first and second gates juxtaposed on opposite sides of said first drain, said first and second gates being operatively connected to the positive gate bus; third and fourth gates juxtaposed on opposite sides of said second drain, said third and fourth gates being operatively connected to the negative gate bus; and positive feedback means including first, second, third and fourth crossover capacitors, said first and second crossover capacitors being operatively connected between the positive gate bus and the positive drain bus at said first gate and said second gate, respectively, and said third and fourth crossover capacitors being operatively connected between the negative gate bus and the negative drain bus at said third gate and said fourth gate, respectively, for minimizing the negative feedback effect of the Miller capacitance beween the positive gate bus and the positive drain bus and said first and second gates and said first drain, and for minimizing the negative feedback effect of the Miller capacitance between the positive gate bus and the positive drain bus and said first and second gates and said second drain.
Claim 2
Dependent Claim
315 words
An improved field effect transistor device of the type having a body of semiconductor material, and a plurality of drains, gates and sources operatively disposed on the body of semiconductor material, said field effect transistor device being connected in a differential input and output configuration including a positive gate bus, a negative gate bus, a positive drain bus, a negative drain bus, and a common source bus, wherein the improvement for a single one of a plurality of alternate parallel connected operating units of said field effect transistor device comprises: a common source operatively connected to the common source bus; first and second drains juxtaposed on opposite sides of said common source, said first drain being operatively connected to the negative drain bus, and said second drain being operatively connected to the positive drain bus; first and second gates juxtaposed on opposite sides of said first drain, said first and second gates being operatively connected to the positive gate bus; third and fourth gates juxtaposed on opposite sides of said second drain, said third and fourth gates being operatively connected to the negative gate bus; and positive feedback means including first, second, third and fourth crossover capacitors, said first and second crossover capacitors being operatively connected between the positive gate bus and the positive drain bus at said first gate and said second gate, respectively, and said third and fourth crossover capacitors being operatively connected between the negative gate bus and the negative drain bus at said third gate and said fourth gate, respectively, for minimizing the negative feedback effect of the Miller capacitance beween the positive gate bus and the positive drain bus and said first and second gates and said first drain, and for minimizing the negative feedback effect of the Miller capacitance between the positive gate bus and the positive drain bus and said first and second gates and said second drain.
Claim 3
Dependent Claim
73 words
The improved field effect transistor device of claim 1 further including fifth and sixth crossover capacitors, said fifth crossover capacitor being operatively connected between the common source bus and the positive gate bus for separating said common source from said first and second gates, and said sixth crossover capacitor being operatively connected between the common source bus and the negative gate bus for separating said common source from said third and fourth gates.
Claim 4
Dependent Claim
50 words
The improved field effect transistor device of claim 2 wherein said first and second crossover capacitors operate to separate said first and second gates, respectively, from said second drain, and wherein said third and fourth crossover capacitors operate to separate said third and fourth gates, respectively, from said first drain.
Claim 5
Dependent Claim
18 words
The improved field effect transistor device of claim 3 wherein the body of semiconductor material comprises gallium arsenide.
References Cited (Backward Citations)
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US4104672A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-11 | 1986-10-11 | 1987-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-11 | 1990-10-11 | 1991-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-11 | 1994-10-11 | 1995-04-12 | $7700.00 | Window Closed / Lapsed |