US4380005A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic zero offset compensating circuit for A/D converter
Assignee: International Business Machines Corp
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Filing: 1980-04-11
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Granted: 1983-04-12
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Expires: 2000-04-11
Abstract
Abstract Disclosed is a dynamic compensation circuit for correcting the residual offset voltage encountered in an analog-to-digital conversion chain. Samples of an analog signal having an average value equal to 0 are provided to a first input of a comparator, the second input of which receives a reference signal generated through a D to A converter under control of a control logic circuit. A sample and hold circuit with the comparator causes a DC offset of the output signal level which is to be dynamically corrected by the compensating circuit of the invention. The DC offset causes the duty cycle to differ from one by an amount ΔDC which will be the error curve signal of the compensation circuit. The compensating circuit reduces the ΔDC to 0 by adding to the signal a DC voltage opposite to and of equal magnitude to the offset voltage level.
Inventors
- 👤 Pierre Debord
- 👤 Jean-Louis Marijon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:59
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/303; H03F1/304; H03M; H03M1/00; H03M1/12; H03M1/124; H03M1/129; H03M1/1295
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
274 words
In an analog device having at least one input and one output and receiving an analog signal with a zero mean value on said input and supplying a signal with a determined relationship with respect to the input signal on its output, an improved compensation circuit for continuously compensating for the zero offset level introduced into the output signal by the device, comprising: means for comparing the level of the output signal with the offset zero level and supplying the sign of the output signal with respect to the offset zero level, said sign being positive if the output signal level exceeds that of the offset zero level and negative if the output signal level is less than the offset zero level; a storing capacitor having a first terminal M and a second terminal connected to ground; charging means for applying a charge current +I to terminal M when the sign of the output signal is negative; discharging means for applying a discharge current -I to terminal M when the sign of the output signal is positive; and means for continuously adding the voltage generated at terminal M in response to the charge and discharge of said storing capacitor to the input signal; and wherein said charging and discharging means include two current sources for supplying currents having the magnitude and sign, respectively, of 2I and -I and which are series-connected between two positive and negative voltage supplies, respectively, having their common point connected to terminal M of said capacitor, said two supplies being always switched on, and steering means for steering 2I to ground when the sign of the output signal is positive.
Claim 2
Dependent Claim
274 words
In an analog device having at least one input and one output and receiving an analog signal with a zero mean value on said input and supplying a signal with a determined relationship with respect to the input signal on its output, an improved compensation circuit for continuously compensating for the zero offset level introduced into the output signal by the device, comprising: means for comparing the level of the output signal with the offset zero level and supplying the sign of the output signal with respect to the offset zero level, said sign being positive if the output signal level exceeds that of the offset zero level and negative if the output signal level is less than the offset zero level; a storing capacitor having a first terminal M and a second terminal connected to ground; charging means for applying a charge current +I to terminal M when the sign of the output signal is negative; discharging means for applying a discharge current -I to terminal M when the sign of the output signal is positive; and means for continuously adding the voltage generated at terminal M in response to the charge and discharge of said storing capacitor to the input signal; and wherein said charging and discharging means include two current sources for supplying currents having the magnitude and sign, respectively, of 2I and -I and which are series-connected between two positive and negative voltage supplies, respectively, having their common point connected to terminal M of said capacitor, said two supplies being always switched on, and steering means for steering 2I to ground when the sign of the output signal is positive.
Claim 3
Dependent Claim
70 words
A circuit according to claim 1, wherein: the analog device is an analog-digital converter which receives at its input a signal to be converted having a zero mean value and supplying the digitally-coded value of the input signal at its output, and in which said signal indicative of the sign of the output signal with respect to the offset zero is supplied by the sign of the coded output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-11 | 1986-10-11 | 1987-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-11 | 1990-10-11 | 1991-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-11 | 1994-10-11 | 1995-04-12 | $7700.00 | Window Closed / Lapsed |