High density dynamic memory cell

Claim 2

A semiconductor memory device including an array of rows and columns of one-transistor dynamic memory cells in a face of a semiconductor body, each cell having a capacitor and having an access transistor with a source-to-drain path and a gate, the memory device comprising: a plurality of semiconductor regions in said face of the semiconductor body, said regions being laterally spaced from one another along said face, each region providing one end of the source-to-drain path of two of the access transistors for two adjacent cells in a column, a plurality of electrodes at said face adjacent said regions, each electrode providing the gate of an access transistor, a plurality of connector areas of said face arranged in columns, each of the areas being for the purpose of making electrical connection separately to one of said regions to thereby provide a connection to two adjacent cells, conductive means extending laterally along said face partially underlying said plurality of electrodes but insulated therefrom by an insulating layer, the conductive means providing a common plate for all of the capacitors of all of the cells, and a plurality of strips of conductive material extending along said face but insulated therefrom, each of the strips making electrical connection to a plurality of said connector areas thereby providing column lines.

Claim 3

A device according to claim 1 wherein each of said regions is one end of a source-to-drain path of two adjacent insulated gate field effect transistors which are said access transistors, and all of said regions in each column are in a straight line and said regions are off set with respect to one another in adjacent columns.

Claim 4

A device according to claim 1 wherein said electrodes are parts of elongated conductive strips forming row lines generally perpendicular to said column lines.

Claim 5

A device according to claim 3 wherein said strips of conductive material forming column lines overly said row lines and said conductive means.

Claim 6

A device according to claim 4 wherein said conductive means overlies a plurality of capacitor areas, one for each cell.

Claim 7

A device according to claim 1 wherein said conductive means is connected to a bias source to create an inverted region at each of said capacitor areas.

Claim 8

A device according to claim 1 wherein the body is predominately P type silicon, said regions are N+ type, said electrodes and conductor segment are polycrystalline silicon, and said conductive material is metal.

Claim 9

A device according to claim 1 wherein said cells are in an array of rows and columns, and there are a plurality of said strips, one extending along each column, and each strip overlies a plurality of separate capacitor areas, one for each cell.

Claim 10

A device according to claim 8 wherein a conductive row line extends along each row and connects to the electrode of each cell in a row.

Claim 11

A device according to claim 9 wherein said conductive row lines are second level polysilicon, said conductor segments are third level polysilicon, and said conductive material is metal.

Claim 12

A device according to claim 10 wherein said conductive material completely covers each of the capacitor areas for alpha particle shielding.

Claim 13

A semiconductor memory device including an array of rows and columns of one-transistor dynamic memory cells in a face of a semiconductor body, each cell having a capacitor and having an access transistor of the insulated gate field-effect type with a source-to-drain path and a gate, the memory device comprising: a plurality of semiconductor regions in said face of the semiconductor body, said regions being laterally spaced from one another along said face with thick field oxide in said face between the regions, each region providing one end of the source-to-drain path of the two access transistors for two adjacent cells in a column, a plurality of electrodes at said face adjacent said regions, each electrode providing the gate of an access transistor, a plurality of connector areas at said face arranged in columns, each of the areas being for the purpose of making electrical connection separately to one of said regions to thereby provide a connection to two adjacent cells, conductive means extending laterally along said face insulated from said electrodes, the conductive means providing an upper plate for all of the capacitors of all of the cells and overlying a capacitor area for each individual cell, the capacitor areas in each of said pairs of adjacent cells having separated on said face from other pairs but not from one another by said thick field oxide, and a plurality of parallel strips of conductive material extending along said face but insulated therefrom, each of the strips making electrical connection to a plurality of said connector areas and thereby providing column lines.

Claim 14

A semiconductor memory device including an array of rows and columns of one-transistor dynamic memory cells in a face of a semiconductor body, each cell having a capacitor and having an access transistor of the insulated gate field-effect type with a source-to-drain path and a gate, the memory device comprising: a plurality of semiconductor regions in said face of the semiconductor body, said regions being laterally spaced from one another along said face with thick field oxide in said face between the regions, each region providing one end of the source-to-drain path of the two access transistors for two adjacent cells in a column, a plurality of electrodes at said face adjacent said regions, each electrode providing the gate of an access transistor, a plurality of connector areas at said face arranged in columns, each of the areas being for the purpose of making electrical connection separately to one of said regions to thereby provide a connection to two adjacent cells, conductive means extending laterally along said face insulated from said electrodes, the conductive means providing an upper plate for all of the capacitors of all of the cells and overlying a capacitor area for each individual cell, the capacitor areas in each of said pairs of adjacent cells having separated on said face from other pairs but not from one another by said thick field oxide, and a plurality of parallel strips of conductive material extending along said face but insulated therefrom, each of the strips making electrical connection to a plurality of said connector areas and thereby providing column lines.

Claim 15

A device according to claim 12 wherein all of said regions in each column are in a straight line and said regions are offset with respect to one another in adjacent columns.

Claim 16

A semiconductor memory device including an array of rows and columns of one-transistor dynamic memory cells in a face of a semiconductor body, each cell having a capacitor and having an access transistor of the insulated gate field-effect type with a source-to-drain path and a gate, the memory device comprising: a plurality of semiconductor regions in said face of the semiconductor body, said regions being laterally separated from one another along said face by thick field oxide recessed in said face between the regions, each region having a pair of said cells therein and including a common N+ area of the face as one end of the source-to-drain path of the two access transistors for two adjacent cells in a column, a plurality of gate electrodes at said face over parts of said regions, each providing the gate of one of the access transistors, a plurality of elongated conductive strips providing column lines, the column lines including connector areas at said face, each of the areas being for the purpose of making electrical connection separately to one of said common N+ areas to thereby provide a connection to two adjacent cells of a column, conductive means extending laterally along said face insulated from said electrodes, the conductive means providing an upper plate for the capacitors of all of the cells and overlying a capacitor area of the semiconductor region for each individual cell, the two capacitor areas in each of said semiconductor regions being at opposite ends of the region and wider than said common N+ area, the two capacitor areas being separated on said face from other semiconductor regions but not from one another by said thick field oxide.

Claim 17

A semiconductor memory device including an array of rows and columns of one-transistor dynamic memory cells in a face of a semiconductor body, each cell having a capacitor and having an access transistor of the insulated gate field-effect type with a source-to-drain path and a gate, the memory device comprising: a plurality of semiconductor regions in said face of the semiconductor body, said regions being laterally separated from one another along said face by thick field oxide recessed in said face between the regions, each region having a pair of said cells therein and including a common N+ area of the face as one end of the source-to-drain path of the two access transistors for two adjacent cells in a column, a plurality of gate electrodes at said face over parts of said regions, each providing the gate of one of the access transistors, a plurality of elongated conductive strips providing column lines, the column lines including connector areas at said face, each of the areas being for the purpose of making electrical connection separately to one of said common N+ areas to thereby provide a connection to two adjacent cells of a column, conductive means extending laterally along said face insulated from said electrodes, the conductive means providing an upper plate for the capacitors of all of the cells and overlying a capacitor area of the semiconductor region for each individual cell, the two capacitor areas in each of said semiconductor regions being at opposite ends of the region and wider than said common N+ area, the two capacitor areas being separated on said face from other semiconductor regions but not from one another by said thick field oxide.

Claim 18

A device according to claim 14 wherein all of said semiconductor regions in each column are in a straight line and said regions are offset with respect to one another in adjacent columns.