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US4376977A
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Computer system with scannable program memory
Assignee: US Philips Corp
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Filing: 1980-08-15
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Granted: 1983-03-15
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Expires: 2000-08-15
Abstract
Abstract A computer system having a program memory for machine instructions to be executed and for other data not included in machine instructions to be executed, also a keyboard, a display device and a processor. In the program memory a quantity of such other data is preceded by a special code from a pre-determined set of not-to-be-executed machine codes plus an adjacent indication giving the address distance between the beginning and the end of the other data in question. A decoder that can address specifically the machine-code set is connected to the instruction register. An address-distance detector is also connected. Together, these elements generate a signal to process the quantity of other data in a specific way and, in particular, not to treat them as further machine instructions. In the design phase of a program, no large capacity memory is required for the text because all relevant information can be stored in a program memory of limited capacity because the machine program has a very compact notation.
Inventors
- 👤 Berend T. J. Bruinshorst
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/30145; G06F9/30149; G06F9/321
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
331 words
A computer system comprising as subsystems: a. a program memory having a sequence of address locations for storing respective machine code data; b. a keyboard; c. a display device for displaying at least one row of alphanumeric characters; d. a processor: and interconnecting means for interconnecting said subsystems; wherein said processor contains at least: an address register having an increment input for addressing the program memory; an instruction register having op code storage means (205) and further storage means (207, 256) for together storing an instruction of at most a predetermined length, said instruction register having an instruction input for coupling to an instruction output of said program memory; first and second instruction decoder means connected to instruction outputs of said opcode storage means and said further storage means, respectively; an execution element having a control input connected to a control output of said first instruction decoder for executing a data processing operation; an address distance detector for detecting a predetermined address distance as traversed in said program memory, the maximum range of said address distance being longer than corresponds to an address distance covered in completely filling said instruction register, said address distance detector having an activation input connected to an activation output of said first instruction decoder for receiving an activation signal under control of a first opcode subset (110001xx) detected, and for thereupon receiving via first means (209) from the instruction register a first address distance to be covered in the program memory and then generating a first control signal (296); wherein said address distance detector has second means (298) for monitoring a relative address distance as covered in the program memory after reception of said activation signal and upon reaching said first address distance generating a deactivation signal (304) and terminating said first control signal; and wherein said processor is responsive to said first control signal for being driven into a non-active mode for information received from the program memory thereof until generation of said deactivation signal.
Claim 2
Dependent Claim
331 words
A computer system comprising as subsystems: a. a program memory having a sequence of address locations for storing respective machine code data; b. a keyboard; c. a display device for displaying at least one row of alphanumeric characters; d. a processor: and interconnecting means for interconnecting said subsystems; wherein said processor contains at least: an address register having an increment input for addressing the program memory; an instruction register having op code storage means (205) and further storage means (207, 256) for together storing an instruction of at most a predetermined length, said instruction register having an instruction input for coupling to an instruction output of said program memory; first and second instruction decoder means connected to instruction outputs of said opcode storage means and said further storage means, respectively; an execution element having a control input connected to a control output of said first instruction decoder for executing a data processing operation; an address distance detector for detecting a predetermined address distance as traversed in said program memory, the maximum range of said address distance being longer than corresponds to an address distance covered in completely filling said instruction register, said address distance detector having an activation input connected to an activation output of said first instruction decoder for receiving an activation signal under control of a first opcode subset (110001xx) detected, and for thereupon receiving via first means (209) from the instruction register a first address distance to be covered in the program memory and then generating a first control signal (296); wherein said address distance detector has second means (298) for monitoring a relative address distance as covered in the program memory after reception of said activation signal and upon reaching said first address distance generating a deactivation signal (304) and terminating said first control signal; and wherein said processor is responsive to said first control signal for being driven into a non-active mode for information received from the program memory thereof until generation of said deactivation signal.
Claim 3
Dependent Claim
45 words
Computer system according to claim 1, in which a first-in, first-out, buffer (FIFO) is present (300) with an input connected to an output of the program memory and a load input to receive continuously said first control signal upon each addressing of the program memory.
Claim 4
Dependent Claim
56 words
Computer system according to claim 1 or 2, in which said second instruction decoder is provided with a first signal output to indicate as an address datum a word read out from the program memory under control of a first specific opcode (C4, 11000100) belonging to said pre-determined opcode set, in cooperation with said first control.
Claim 5
Dependent Claim
56 words
Computer system according to claim 1 or 2, in which said second instruction is provided with a second signal output to identify a word read-out from said program memory as a data element, under the control of a second specific opcode (C5, 11000101) belonging to said pre-determined opcode set, in cooperation with said first control signal.
Claim 6
Dependent Claim
57 words
Computer system according to claim 1 or 2, in which said second instruction decoder is provided with a third signal output to identify a word read out from said program memory as text data, under the control of a third specific opcode (C6, 11000110) belonging to said pre-determined opcode set, in cooperation with said first control signal.
Claim 7
Dependent Claim
57 words
Computer system according to claims 1 or 2, in which said second instruction decoder is provided with a fourth signal output to identify a word read out from said program memory as a title, under the control of a fourth specific opcode (C7, 11000111) belonging to said pre-determined opcode set, in cooperation with said first control signal.
Claim 8
Dependent Claim
50 words
Computer system according to claims 1 or 2, in which said de-activating signal (304) acts as a first stop-signal (294) for said address register and that said keyboard is provided with fourth means (e.g. spacing bar) to make said first stop-signal inoperative by means of a second control signal (270).
Claim 9
Dependent Claim
63 words
Computer system according to claim 7, in which said keyboard is provided with fifth means, with the aid of a third control signal, to render said first stop-signal continuously inoperative, and in which address-comparing means are present to terminate said third control signal and to generate a second stop-signal for said address register when a final address is reached by said address register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-03-14 | 1986-09-13 | 1987-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-03-14 | 1990-09-13 | 1991-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-03-14 | 1994-09-13 | 1995-03-15 | $7700.00 | Window Closed / Lapsed |