Arbitration controller providing for access of a common resource by a plurality of central processing units

Claim 1

An arbitration controller providing for equal priority sharing of a common resource by a plurality of CPUs, said arbitration controller comprising: means for initialization providing a first signal; a plurality of arbitration circuits including a first, at least one successive and a last arbitration circuit; said means for initialization connected to at least one of said arbitration circuits; a plurality of CPU buses, each connected between a particular CPU and a particular arbitration circuit on a one for one basis, each CPU bus including a control portion and an address/data portion; a common bus connected between each of said CPUs and said resource via said particular arbitration circuit for the transmission of information between said resource and any of said plurality of CPUs via said address/data portion of said CPU bus; bus means for connecting said common bus to each of said plurality of CPU buses in a tri-state fashion; a plurality of circuit connections including a circuit connection between each arbitration circuit and each successive arbitration circuit, said last arbitration circuit connected to said first arbitration circuit, thereby forming a completed ring connection for propagating said first signal from one arbitration circuit to another arbitration circuit in a circular fashion; each arbitration circuit connected to said control portion of said particular CPU bus and operated in response to said first signal and to a common bus request signal from its corresponding CPU to produce a second signal for allowing said corresponding one of said plurality of CPUs access to said resource via said common bus; each said arbitration circuit including: first gating means operated to propagate said first signal along said ring connection at a relatively high rate of speed; latching means operated in response to said common bus request signal of said corresponding CPU to produce said second signal for allowing said CPU to access said resource via said common and CPU buses; second gating means operated in response to said operated latching means and in response to said propagated first signal to propagate a third signal from each arbitration circuit to each successive arbitration circuit; and said first signal propagating through each of said arbitration circuits in said ring connection to successively enable said CPU access to said resource via said common bus, while said third signal permitting said successive arbitration circuits to establish priority for subsequent access of said resource simultaneously with a present access of said resource.