Patent US4373201A successfully refreshed from Google Patents.
US4373201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fail safe digital timer
Assignee: Honeywell Inc
•
Filing: 1980-11-28
•
Granted: 1983-02-08
•
Expires: 2000-11-28
Abstract
Abstract A fail safe digital timer is provided by having a pair of similar counters counting the output of a single clock means. The clock means provides clock pulses and complimentary clock pulses to the two counters and the outputs of the counters are compared. If the two counters are properly operating the comparison will provide a continuous stream of pulses at a frequency equal to the frequency of the clock means for the timer. The failure of any of the components in the system cause the output of the comparator means to either become a constant logic 1 or a constant logic 0.
Inventors
- 👤 John E. Bohan, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 05:58
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1604; F; F23; F23N; F23N5/00; F23N5/20; F23N5/203; F23N5/24; F23N5/242; G04; G04F; G04F1/00; G04F1/005; G06F11/1608
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
188 words
A fail safe digital timer, including: clock means having output means providing clock pulses and complimentary clock pulses; first counter means connected to said clock output means to receive said clock pulses with said first counter means having output means to provide first counter codes; second counter means connected to said clock output means to receive said complimentary clock pulses with said second counter means having output means to provide second counter codes; comparator means connected to the output means of said counter means to compare said first and said second counter codes; said comparator means having a repetitive output signal upon both said counter means successfully counting the clock pulses and the complimentary clock pulses; said repetitive output signal ceasing upon the failure of the proper outputs being present from said clock means, said counter means, and said comparator means; and load means connected to said repetitive output signal and the counter codes from said second counting means; said load means being responsive to the presence or absence of said repetitive output signal from said comparator means along with the counter codes from said second counter means.
Claim 2
Dependent Claim
188 words
A fail safe digital timer, including: clock means having output means providing clock pulses and complimentary clock pulses; first counter means connected to said clock output means to receive said clock pulses with said first counter means having output means to provide first counter codes; second counter means connected to said clock output means to receive said complimentary clock pulses with said second counter means having output means to provide second counter codes; comparator means connected to the output means of said counter means to compare said first and said second counter codes; said comparator means having a repetitive output signal upon both said counter means successfully counting the clock pulses and the complimentary clock pulses; said repetitive output signal ceasing upon the failure of the proper outputs being present from said clock means, said counter means, and said comparator means; and load means connected to said repetitive output signal and the counter codes from said second counting means; said load means being responsive to the presence or absence of said repetitive output signal from said comparator means along with the counter codes from said second counter means.
Claim 3
Dependent Claim
23 words
A fail safe digital timer as disclosed in claim 1 wherein said clock pulses and said complimentary clock pulses are digital logic pulses.
Claim 4
Dependent Claim
34 words
A fail safe digital timer as disclosed in claim 2 wherein said first and said second counter means are similar binary counters; and said first and said second counter codes are digital logic codes.
Claim 5
Dependent Claim
40 words
A fail safe digital timer as disclosed in claim 3 wherein said comparator means repetitive output signal is a continuous series of pulses equal in frequency to the frequency of said clock pulses when said digital timer is functioning properly.
Claim 6
Dependent Claim
39 words
A fail safe digital timer as disclosed in claim 4 wherein said clock means includes a NOT gate in said clock output means to provide the complimentary digital clock pulses; and a signal source included in said clock means.
Claim 7
Dependent Claim
37 words
A fail safe digital timer as disclosed in claim 4 wherein said load means includes logic means responsive to the counter pulses from said second counter means to establish a time of operation of said load means.
Claim 8
Dependent Claim
56 words
A fail safe digital timer as disclosed in claim 6 wherein said load means further includes flame responsive sensor means having a digital logic output which is compared with an output from said logic means with the resultant compared outputs connected to operate said load means; and fuel control means controlled by said resultant compared outputs.
Claim 9
Dependent Claim
37 words
A fail safe digital timer as disclosed in claim 7 wherein said load means includes an OR gate to combine the flame sensor digital logic output and the logic means output to control said fuel control means.
Claim 10
Dependent Claim
27 words
A fail safe digital timer as disclosed in claim 8 wherein said fuel control means includes solid state switch means to energize electromagnetically operated fuel control means.
Claim 11
Dependent Claim
32 words
A fail safe digital timer as disclosed in claim 9 wherein said solid state switch means is a silicon controlled rectifier and said said electromagnetically operated fuel control means includes a relay.
References Cited (Backward Citations)
US3155939A
Cited
US3618015A
Cited
US3845282A
Cited
US3898444A
Cited
US4096396A
Cited
US4255809A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-07 | 1986-08-09 | 1987-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-07 | 1990-08-09 | 1991-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-07 | 1994-08-09 | 1995-02-08 | $7700.00 | Window Closed / Lapsed |