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US4371923A
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Computer system architecture
Assignee: Individual
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Filing: 1977-12-14
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Granted: 1983-02-01
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Expires: 1997-12-14
Abstract
Abstract An integrated circuit data processor arrangement is provided having a data processor architecture that can be implemented entirely of integrated circuits. The combination of an integrated circuit read only memory and an integrated circuit alterable memory and the ability to process operands stored in the alterable memory under control of instructions stored in the read only memory facilitates a fully integrated circuit data processor. Other data processor features that facilitate the fully integrated circuit architecture include integrated circuit paging logic and a storing arrangement for storing information in the main memory. Systems applications of the integrated circuit computer includes control of machines, control of photo-optical devices, and interaction with an operator.
Inventors
- 👤 Gilbert P. Hyatt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:17
CPC Classifications
B; B60; B60R; B60R16/00; B60R16/02; B60R16/037; B60R16/0373; F; F21; F21V; F21V23/00; G; G01; G01S; G01S15/00; G01S15/88; G01S15/89; G01S15/8906; G01S15/8965; G01S15/897; G01S15/8977; G01S7/00; G01S7/52; G01S7/52017; G01S7/52023; G01S7/52025; G01S7/52026; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/13306; G02F1/13318; G03; G03F; G03F9/00; G03F9/70; G03F9/7049; G03F9/7088; G04; G04G; G04G99/00; G04G99/006; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/19; G05B19/33; G05B19/35; G05B19/351; G05B19/408; G05B19/4083; G05B19/4086; G05B19/409; G05B19/4093; G05B19/414; G05B19/4142; G06; G06J; G06J1/00; G07; G07G; G07G1/00; G07G1/12; G10; G10L; G10L19/00; G11; G11C; G11C11/00; G11C11/56; G11C11/565; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3431; G11C19/00; G11C19/28; G11C19/287; G11C19/34; G11C19/36; G11C27/00; G11C27/04; G05B2219/00; G05B2219/30; G05B2219/33; G05B2219/33182; G05B2219/34; G05B2219/34023; G05B2219/34098; G05B2219/34471; G05B2219/34472; G05B2219/35; G05B2219/35262; G05B2219/35263; G05B2219/35373; G05B2219/35431; G05B2219/35436; G05B2219/35453; G05B2219/35472; G05B2219/35554; G05B2219/36; G05B2219/36152; G05B2219/36333; G05B2219/36366; G05B2219/36379; G05B2219/36503; G05B2219/36546; G05B2219/41; G05B2219/41021; G05B2219/42; G05B2219/42237; G05B2219/45; G05B2219/45214; G05B2219/45215; G05B2219/49; G05B2219/49221; G05B2219/50; G05B2219/50047; G05B2219/50048; G05B2219/50083; G05B2219/50151; G11C7/00; G11C7/16; Y; Y02; Y02P; Y02P90/00; Y02P90/02
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
112 words
An integrated circuit data processor, said data processor including: an integrated circuit read only main memory for storing a program, said main memory including a plurality of word locations assigned to a plurality of said main memory, each word location storing an instruction of said program integrated circuit processing logic for processing input data in response to certain of said instructions of the program stored in said integrated circuit read main memory; and integrated circuit read only main memory paging logic for selecting one of the plurality of pages of said main memory, said one selected page having included therein the word location of a certain instruction used in processing said data.
Claim 2
Dependent Claim
112 words
An integrated circuit data processor, said data processor including: an integrated circuit read only main memory for storing a program, said main memory including a plurality of word locations assigned to a plurality of said main memory, each word location storing an instruction of said program integrated circuit processing logic for processing input data in response to certain of said instructions of the program stored in said integrated circuit read main memory; and integrated circuit read only main memory paging logic for selecting one of the plurality of pages of said main memory, said one selected page having included therein the word location of a certain instruction used in processing said data.
Claim 3
Dependent Claim
78 words
The data processor as set forth in claim 1 above, further comprising: an integrated circuit alterable memory for temporarily storing, in word registers, the data processed by said processing logic, said a multiple number of said word registers having a plurality of pages of alterable memory and integrated circuit alterable memory paging logic for selecting the one of the plurality of pages of said alterable memory having the word registers which were used for storing the processed data.
Claim 4
Dependent Claim
36 words
The data processor as set forth in claim 1 above, further comprising communication means for communicating the processed data to an apparatus in a remote location in response to a said one of said certain instructions.
References Cited (Backward Citations)
US3548172A
Cited
US3646522A
Cited
US3702988A
Cited
US3740723A
Cited
US4021656A
Cited
US3980992A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-31 | 1986-08-02 | 1987-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-31 | 1990-08-02 | 1991-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-31 | 1994-08-02 | 1995-02-01 | $7700.00 | Window Closed / Lapsed |