Patent US1947796A successfully refreshed from Google Patents.
Patent US4369515A successfully refreshed from Google Patents.
US4369515A
Expired / Lapsed
US
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Clock synchronization circuit
Assignee: AG Communication Systems Corp
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Filing: 1980-10-06
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Granted: 1983-01-18
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Expires: 2000-10-06
Abstract
Abstract A circuit which monitors the frequency of an incoming signal and synchronizes an internally generated clock signal to the incoming signal. A retriggerable monostable multivibrator monitors the incoming signal which is synchronized by means of a phase lock loop circuit to a signal generated by a voltage controlled multivibrator. A crystal oscillator provides clock signals upon detection of failure of the incoming clock signal.
Inventors
- 👤 Jose L. Valdes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:39
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
237 words
A clock synchronization circuit for use in a telephone switching system including a digital line operated to provide bi-polar digital data of a variable frequency, conversion means connected to said digital line, operated to convert said bi-polar digital data to uni-polar digital data, clock derivation means connected to said conversion means operated to derive clock signals from said uni-polar digital data, and a digital network, said synchronization circuit comprising: a retriggerable monostable multi-vibrator connected to said clock derivation means operated in response to said derived clock signals having a frequency above a first predetermined value to generate a first enable signal, and further operated in response to said derived clock signals having a frequency below a predetermined value to generate a second enable signal; first clock signal generating means connected to said retriggerable monostable multi-vibrator, operated in response to said derived clock signals to generate a first clock signal having a frequency related to the frequency of said derived clock signals; second clock signal generating means operated to generate a second clock signal of a predetermined frequency; and gating means connected to said retriggerable monostable multi-vibrator, said first clock signal generating means and said second clock signal generating means, operated in response to said first enable signal to gate said first clock signal to said digital network, and further operated in response to said second enable signal to gate said second clock signal to said digital network.
Claim 2
Dependent Claim
237 words
A clock synchronization circuit for use in a telephone switching system including a digital line operated to provide bi-polar digital data of a variable frequency, conversion means connected to said digital line, operated to convert said bi-polar digital data to uni-polar digital data, clock derivation means connected to said conversion means operated to derive clock signals from said uni-polar digital data, and a digital network, said synchronization circuit comprising: a retriggerable monostable multi-vibrator connected to said clock derivation means operated in response to said derived clock signals having a frequency above a first predetermined value to generate a first enable signal, and further operated in response to said derived clock signals having a frequency below a predetermined value to generate a second enable signal; first clock signal generating means connected to said retriggerable monostable multi-vibrator, operated in response to said derived clock signals to generate a first clock signal having a frequency related to the frequency of said derived clock signals; second clock signal generating means operated to generate a second clock signal of a predetermined frequency; and gating means connected to said retriggerable monostable multi-vibrator, said first clock signal generating means and said second clock signal generating means, operated in response to said first enable signal to gate said first clock signal to said digital network, and further operated in response to said second enable signal to gate said second clock signal to said digital network.
Claim 3
Dependent Claim
125 words
A clock synchronization circuit as claimed in claim 1, wherein said first clock signal generating means is further operated to generate a clock compare signal, said clock synchronization circuit further comprising: detection means connected to said retriggerable monostable multi-vibrator, and said first clock signal generating means, operated in response to a difference in frequency between said derived clock signal and said clock compare signal to generate an error signal; said first clock signal generating means further operated in response to said error signal to adjust the frequency of said clock compare signal to equal the frequency of said derived clock signal; said first clock signal generating means further operated in response to said error signal to proportionately adjust the frequency of said first clock signal.
Claim 4
Dependent Claim
133 words
A clock synchronization circuit as claimed in claim 1, wherein said first clock signal generating means is further operated to generate a clock compare signal, said clock synchronization circuit further comprising: detection means connected to said retriggerable monostable multi-vibrator, and said first clock signal generating means, operated in response to a difference in phase between said derived clock signal and said clock compare signal to generate an error signal; said first clock signal generating means further operated in response to said error signal to adjust the phase of said clock compare signal to equal the phase of said derived clock signal; said first clock signal generating means further operated in response to said error signal to adjust the phase of said first clock signal to equal the phase of said derived clock signal.
Claim 5
Dependent Claim
65 words
A clock synchronization circuit as claimed in claims 2 or 3, wherein said detection means comprise: a phase/frequency detector, operated in response to said difference in phase or frequency between said derived clock signal and said clock compare signal to generate a signal representative of said difference; and filter means connected to said phase/frequency detector, operated to shape said difference signal, into said error signal.
Claim 6
Dependent Claim
20 words
A clock synchronization circuit as claimed in claim 1, wherein said second clock signal generating means comprise a crystal oscillator.
Claim 7
Dependent Claim
36 words
A clock synchronization circuit as claimed in claims 2 or 3, wherein said first clock signal generating means comprise: a voltage controlled multivibrator operated to generate said first clock signals within a predetermined range of frequencies.
Claim 8
Dependent Claim
46 words
A clock synchronization circuit as claimed in claim 6, wherein said first clock signal generating means further comprise: division means connected to said voltage controlled multivibrator, operated to divide the frequency of said first clock signal by a binary integer, thereby generating said clock compare signal.
Claim 9
Dependent Claim
25 words
A clock synchronization circuit as claimed in claim 7, wherein said division means operate to divide the frequency of said first clock signal by 4.
Claim 10
Dependent Claim
120 words
A clock synchronization circuit as claimed in claim 6, wherein said gating means comprise a first gate circuit connected to said retriggerable monostable multivibrator and said voltage controlled multivibrator, a second gate circuit connected to said retriggerable monostable multivibrator and said crystal oscillator, and a third gate circuit connected to said first and said second gate circuits, said first gate circuit operated in response to said first enable signal to gate said clock signal generated by said voltage controlled multivibrator to said network via said third gate circuit, and said second gate circuit operated in response to said second enable signal to gate said clock signal generated by said crystal oscillator to said digital network via said third gate circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-17 | 1986-07-19 | 1987-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-17 | 1990-07-19 | 1991-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-17 | 1994-07-19 | 1995-01-18 | $7700.00 | Window Closed / Lapsed |