Device for reading a quantity of electric charges and charge-filter equipped with said device

Claim 1

A device for reading a quantity of electric charges, comprising a first transistor (Q 2 ) and a second transistor (Q 3 ), each having source, drain and gate, said transistors being connected at a common point (A) with the drain of one transistor being connected to the source of the other transistor in series connection, said series being connected to a point (B) of arrival of the quantity of charges to be read, a first capacitor (C A ) having one terminal connected to the common point (A) of the two transistors (Q 2 , Q 3 ), control circuit means connected to the gates of the two transistors (Q 2 , Q 3 ) for charging the first capacitor (C A ) and for maintaining the first transistor (Q 2 ) in the saturating mode, and thus maintaining an essentially constant potential at the point of arrival (B) at the time of inflow of the charges, the effect of said inflow being to produce a variation in potential at the common point (A) and thereby delivering the reading signal at the common point (A).

Claim 2

A device for reading a quantity of electric charges, comprising a first transistor (Q 2 ) and a second transistor (Q 3 ), each having source, drain and gate, said transistors being connected at a common point (A) with the drain of one transistor being connected to the source of the other transistor in series connection, said series being connected to a point (B) of arrival of the quantity of charges to be read, a first capacitor (C A ) having one terminal connected to the common point (A) of the two transistors (Q 2 , Q 3 ), control circuit means connected to the gates of the two transistors (Q 2 , Q 3 ) for charging the first capacitor (C A ) and for maintaining the first transistor (Q 2 ) in the saturating mode, and thus maintaining an essentially constant potential at the point of arrival (B) at the time of inflow of the charges, the effect of said inflow being to produce a variation in potential at the common point (A) and thereby delivering the reading signal at the common point (A).

Claim 3

A device for reading a quantity of electric charges, comprising a first transistor (Q 2 ) and a second transistor (Q 3 ), each having source, drain and gate with the drain of one transistor being connected to the source of the other transistor in series, said series connection being connected to a point (B) of arrival of the quantity of charges to be read, a first capacitor (C A ) having one terminal connected to the common point (A) of the two transistors (Q 2 , Q 3 ), control circuit means connected to the gates of the two transistors (Q 2 , Q 3 ) for charging the first capacitor (C A ) and for maintaining the first transistor (Q 2 ) in the saturating mode, and thus maintaining an essentially constant potential at the point of arrival (B) at the time of inflow of the charges, the effect of said inflow being to produce a variation in potential at the common point (A) and thereby delivering the reading signal at the common point (A); wherein the control circuit receives a first constant potential (V DD ) and comprises: a third transistor (Q 4 ) connected between said constant potential (V DD ) and a second terminal of the second transistor (Q 3 ); a fourth transistor (Q 5 ) and a fifth transistor (Q 6 ), said transistors being connected in series between the first constant potential (V DD ) and a reference potential of the device; a second capacitor (C E ) connected between the gate of the first transistor (Q 2 ) and a common point (E) of the fourth (Q 5 ) and fifth (Q 6 ) transistors, the gate of the second transistor (Q 3 ) being connected to said common point (E); a third capacitor (C F ) connected between the gate of the first transistor (Q 2 ) and a common point (F) of the second (Q 3 ) and third (Q 4 ) transistors.

Claim 4

A device for reading a quantity of electric charges, comprising a first transistor (Q 2 ) and a second transistor (Q 3 ), each having source, drain and gate with the drain of one transistor being connected to the source of the other transistor in series, said series connection being connected to a point (B) of arrival of the quantity of charges to be read, a first capacitor (C A ) having one terminal connected to the common point (A) of the two transistors (Q 2 , Q 3 ), control circuit means connected to the gates of the two transistors (Q 2 , Q 3 ) for charging the first capacitor (C A ) and for maintaining the first transistor (Q 2 ) in the saturating mode, and thus maintaining an essentially constant potential at the point of arrival (B) at the time of inflow of the charges, the effect of said inflow being to produce a variation in potential at the common point (A) and thereby delivering the reading signal at the common point (A); wherein the control circuit receives a first constant potential (V DD ) and comprises: a third transistor (Q 4 ) connected between said constant potential (V DD ) and a second terminal of the second transistor (Q 3 ); a fourth transistor (Q 5 ) and a fifth transistor (Q 6 ), said transistors being connected in series between the first constant potential (V DD ) and a reference potential of the device; a second capacitor (C E ) connected between the gate of the first transistor (Q 2 ) and a common point (E) of the fourth (Q 5 ) and fifth (Q 6 ) transistors, the gate of the second transistor (Q 3 ) being connected to said common point (E); a third capacitor (C F ) connected between the gate of the first transistor (Q 2 ) and a common point (F) of the second (Q 3 ) and third (Q 4 ) transistors.