Metal-insulator-semiconductor compatible charge transfer device memory system

Claim 2

A charge transfer device digital data processing system comprising in combination on a semiconductor chip: charge transfer device shift register means having an output diode for entering data therein and an output diode charge sink; first clock pulse operable insulated gate field-effect transistor ratioless inverter circuit means selectively connected to said input diode for operating said input diode to enter charge into said shift register responsive to voltages corresponding to digital logic input signal levels; second clock pulse operable insulated gate field-effect transistor ratioless inverter circuit means connected to said output diode, said second inverter circuit means including a first insulated gate field-effect transistor means for precharging said output diode to a reference potential, said output diode responsive to absence of charge corresponding to a logic 0 in the last bit of said shift register to discharge to a Second voltage level, said output diode further responsive to presence of charge corresponding to a logic 1 in the last bit of the shift register to remain charged substantially at said reference voltage, said second inverter circuit means adapted to respond to said discharged and charged conditions of said output diode to produce respectively a logic 0 or a logic 1 output signal level.

Claim 3

A charge transfer device digital data processing system according to claim 1, further including insulated gate field-effect transistor switch means for selectively connecting output signals produced by said second inverter means to said first ratioless inverter circuit means for recirculation of data through said shift register means.

Claim 4

A charge transfer device digital data processing system as set forth in claim 1, wherein said detector means further includes second insulated gate field-effect transistor means for selectively coupling the detector output to circuit ground, said second transistor means including a first transistor for precharging the output of said detector to a reference potential and a second transistor having a gate electrode connected to said output diode, a first terminal connected to circuit ground and a second terminal connected to the output of said detector whereby responsive to said diode remaining charged to said reference potential said second transistor is biased off whereas responsive to said diode being discharged to said second potential, said second transistor is biased on, thereby connecting said precharged output to circuit ground.

Claim 5

In a data processing system including metal insulator semiconductor logic circuitry operably responsive to first and second non-overlapping clocks respectively having a preselected frequency, a dynamic semiconductor charge transfer device memory compatible with said metal-insulator-semiconductor logic circuitry and having an effective data rate equal to said preselected frequency, comprising in combination on a chip: a first set of n-parallel semiconductor charge transfer device shift registers on said chip, each shift register having an input and output diode associated therewith, said shift registers operably responsive to an n-phase overlapping clock system, said shift registers being disposed on said chip such that the input diode of each shift register is spaced from the input diode of the adjacent shift register in the direction of charge propagation along said shift registers by a distance corresponding to one phase of said n-phase clock; insulated gate field-effect transistor input means connected to said input diodes of said n shift registers and responsive to said first clock and respective overlapping portions of said n-phase clock system to enter binary input data into said shift registers during respective phases of said n-phase clock system; and insulated gate field-effect transistor charge detector means on said chip adjacent said n shift registers, said detector means effective to precharge said output diodes to a reference value during said second clock, whereby the voltage levels of said output diodes are respectively changed during the subsequent individual phases of the n-phase clock system by an amount corresponding to the binary data detected, said detector means operably responsive to the respective voltage levels of said output diodes, to produce output voltage levels corresponding to the binary logic levels of the detected charges in a sequence corresponding to the sequence of said binary input data.

Claim 6

In a data processing system including metal insulator semiconductor logic circuitry operably responsive to first and second non-overlapping clocks respectively having a preselected frequency, a dynamic semiconductor charge transfer device memory compatible with said metal-insulator-semiconductor logic circuitry and having an effective data rate equal to said preselected frequency, comprising in combination on a chip: a first set of n-parallel semiconductor charge transfer device shift registers on said chip, each shift register having an input and output diode associated therewith, said shift registers operably responsive to an n-phase overlapping clock system, said shift registers being disposed on said chip such that the input diode of each shift register is spaced from the input diode of the adjacent shift register in the direction of charge propagation along said shift registers by a distance corresponding to one phase of said n-phase clock; insulated gate field-effect transistor input means connected to said input diodes of said n shift registers and responsive to said first clock and respective overlapping portions of said n-phase clock system to enter binary input data into said shift registers during respective phases of said n-phase clock system; and insulated gate field-effect transistor charge detector means on said chip adjacent said n shift registers, said detector means effective to precharge said output diodes to a reference value during said second clock, whereby the voltage levels of said output diodes are respectively changed during the subsequent individual phases of the n-phase clock system by an amount corresponding to the binary data detected, said detector means operably responsive to the respective voltage levels of said output diodes, to produce output voltage levels corresponding to the binary logic levels of the detected charges in a sequence corresponding to the sequence of said binary input data.

Claim 7

In a data processing system including metal-insulator-semiconductor logic circuitry operably responsive to first and second non-overlapping clocks respectively having a preselected frequency, a dynamic charge transfer device memory compatible with said logic circuitry and having an effective data rate equal to said preselected frequency comprising in combination on a chip: input terminals for receiving said first and second non-overlapping clocKs; clock generator means on said chip for receiving said first clock and generating, responsive thereto, an n phase overlapping clock system, each phase thereof having a frequency of 1/n that of said first clock, wherein n is an integer; a first set of n parallel charge transfer device shift registers on said chip, each shift register having an input and output diode associated therewith, said shift registers being disposed on said chip such that the input diode of each shift register is laterally spaced from the input diode of the adjacent shift register in the direction of data propogation by a distance corresponding to one phase of said n phase clock; insulated gate field-effect transistor input means connected to said n shift registers for multiplexing binary input data thereon responsive to said second clock and an overlapping portion of said n phase clock system; insulated gate field-effect transistor charge detector means on said chip adjacent said n shift registers, said detector means effective to precharge said output diodes to a reference value during said second clock, whereby the voltage level of said output diodes is changed during the subsequent first phase clock by an amount corresponding to the binary data detected, said detector means operable to produce, responsive to the voltage level of said output diodes, and output voltage corresponding to the logic level of the detected charge; and means for connecting the output of said detector means to said input means for recirculating data.

Claim 8

In a data processing system including metal-insulator-semiconductor logic circuitry operably responsive to first and second non-overlapping clocks respectively having a preselected frequency, a dynamic charge transfer device memory compatible with said logic circuitry and having an effective data rate equal to said preselected frequency comprising in combination on a chip: input terminals for receiving said first and second non-overlapping clocKs; clock generator means on said chip for receiving said first clock and generating, responsive thereto, an n phase overlapping clock system, each phase thereof having a frequency of 1/n that of said first clock, wherein n is an integer; a first set of n parallel charge transfer device shift registers on said chip, each shift register having an input and output diode associated therewith, said shift registers being disposed on said chip such that the input diode of each shift register is laterally spaced from the input diode of the adjacent shift register in the direction of data propogation by a distance corresponding to one phase of said n phase clock; insulated gate field-effect transistor input means connected to said n shift registers for multiplexing binary input data thereon responsive to said second clock and an overlapping portion of said n phase clock system; insulated gate field-effect transistor charge detector means on said chip adjacent said n shift registers, said detector means effective to precharge said output diodes to a reference value during said second clock, whereby the voltage level of said output diodes is changed during the subsequent first phase clock by an amount corresponding to the binary data detected, said detector means operable to produce, responsive to the voltage level of said output diodes, and output voltage corresponding to the logic level of the detected charge; and means for connecting the output of said detector means to said input means for recirculating data.

Claim 9

A dynamic charge transfer device memory as set forth in claim 5 wherein said input means comprise first and second series connected insulated gate field-effect transistors, the common terminal of said first and second transistors being connected to all of said input diodes of said n shift registers, and a third insulated gate field-effect transistor having a source for receiving input data, a drain connected to the gate of said second transistor, and a gate electrode connected to said second clock, whereby responsive to said second clock the complement of the data present at the source of said third transistor is produced at the juncture of said first and second transistors such that charge corresponding to successive input bits is sequentially entered into successive ones of said n shift registers during the successive overlap portions of said overlapping n phase clock system, thereby producing an effective data rate equal to the data rate of said first clock.

Claim 10

A dynamic charge transfer device memory as set forth in claim 6 including a second set of n parallel shift registers with associated insulated gate field-effect transistor input means and insulated gate field-effect transistor detector means; means for connecting the output of said first set of n charge transfer device shift registers to the input of said second set of n parallel shift registers; and means for connecting the output of said second set of n shift registers to the input of said first set of n shift registers.

Claim 11

A dynamic charge transfer device memory as set forth in claim 7 wherein said connecting means comprises a doped interconnect region in the surface of said chip between said first and second sets of shift registers, said interconnect having a width on the order of the width of one charge transfer device shift register.

Claim 12

In a digital data metal insulator semiconductor processing system operable in responsive to a master synchronization clock of a preselected frequency, a charge transfer device memory configuration having a data rate equal to said master synchronization clock and operably responsive thereto, comprising in combination on a single semiconductor chip; first clock generating means for receiving said master clock and generating, responsive thereto, first and second nonoverlapping clocks respectively having a frequency of one-half that of said master clock; secOnd clock generating means for receiving said first clock and generating, responsive thereto, an n-phase overlapping clock system suitable for controlling charge transfer device shift registers, each phase thereof having a frequency of 1/2n the frequency of said master clock, wherein n is an integer; and a plurality of parallel charge transfer device shift register units on said chip, each shift register unit having first and second sets of parallel shift registers of n shift registers each, each shift register unit having ratioless dynamic input means on said chip for multiplexing input data onto said first and second sets of shift registers, and output ratioless dynamic detector means on said chip for sequentially detecting the charge at the output of each shift register of said first and second sets of said shift register unit and demultiplexing said data to provide a voltage corresponding to the binary logic level of detected charge, whereby the effective clock rate of said shift register unit is the same as the clock rate of said master clock.

Claim 13

In a digital data metal insulator semiconductor processing system operable in responsive to a master synchronization clock of a preselected frequency, a charge transfer device memory configuration having a data rate equal to said master synchronization clock and operably responsive thereto, comprising in combination on a single semiconductor chip; first clock generating means for receiving said master clock and generating, responsive thereto, first and second nonoverlapping clocks respectively having a frequency of one-half that of said master clock; secOnd clock generating means for receiving said first clock and generating, responsive thereto, an n-phase overlapping clock system suitable for controlling charge transfer device shift registers, each phase thereof having a frequency of 1/2n the frequency of said master clock, wherein n is an integer; and a plurality of parallel charge transfer device shift register units on said chip, each shift register unit having first and second sets of parallel shift registers of n shift registers each, each shift register unit having ratioless dynamic input means on said chip for multiplexing input data onto said first and second sets of shift registers, and output ratioless dynamic detector means on said chip for sequentially detecting the charge at the output of each shift register of said first and second sets of said shift register unit and demultiplexing said data to provide a voltage corresponding to the binary logic level of detected charge, whereby the effective clock rate of said shift register unit is the same as the clock rate of said master clock.

Claim 14

A charge transfer device memory configuration as set forth in claim 9, wherein said first clock generator means comprises a D-type flip-flop.

Claim 15

A charge transfer device memory configuration as set forth in claim 10, wherein said input means comprises first and second dynamic ratioless inverters coupled respectively to said first and second sets of shift registers, each of said inverters having an output connecting in common all of the input diodes of the parallel shift registers associated therewith, and having a gating transistor responsive to said second clock connecting each of said first and second inverters to an input terminal, said first and second inverters effective to gate input data to one of the shift registers associated therewith responsive to said second clock, said second inverter coupled to said input terminal by a third inverter responsive to said first clock whereby alternate bits of input data are delayed by one clock time before they are transferred to said second inverter.

Claim 16

A charge transfer device memory configuration as set forth in claim 11, wherein said output detector includes first and second means for precharging the output diodes of each shift register of said first and second sets to a reference potential, whereby the voltage potential at said diodes varies responsive to the amount of charge subsequently shifted to the output bit of the corresponding charge transfer device shift register; and transistor means responsive to the voltage potential at said output diodes and said first clock, said transistor means coupled to an output terminal and effective to control the output voltage thereat to either a logic 1 or a logic 0 level, depending on the voltage potential at the output diode of the charge transfer device being detected, said first precharge means coupled to said output by a delay stage responsive to said second clock, thereby producing an output having a data rate equal to said master clock.

Claim 17

A charge transfer device memory configuration as set forth in claim 12, wherein said first and second precharge means respectively include a single insulated gate field-effect transistor, the source of which is connected to each output diode of the charge transfer device shift registers associated therewith, the gate of which is disposed for receiving said second clock, and the drain of which is connected to said first clock, effectively coupling said drain to circuit ground during the interval said second clock is on.

Claim 18

A charge transfer device memory configuration as set forth in claim 13, wherein said transistor means comprises a first insulated gate field-effect transistor having its source and gate connected to said first clock and having its drain connected to an output terminal, and a second insulated gate field-effect transistor having one terminal connected to said output terminal, the other terminal of which is connected to said first clock, thE gate of which is connected to each of said output diodes associated therewith, whereby during said first clock the voltage potential at the output diode of the charge transfer device shift register being detected controls conduction of said second insulated gate field-effect transistor whereby said output terminal is either shorted to circuit ground at the termination of said first clock or remains at a potential that is near the amplitude of said first clock.

Claim 19

A charge transfer device memory configuration as set forth in claim 14 further including means for connecting the voltage at said output terminal of said detector back to said input means thereby enable recirculation of data.

Claim 20

A charge transfer device memory configuration as set forth in claim 15, wherein said connecting means comprises a doped interconnect region in the surface of said chip adjacent to said shift register unit of parallel charge transfer device shift registers.

Claim 21

A charge transfer device memory configuration as set forth in claim 16 further including means for selectively connecting the output from the detector of said first shift register unit to the input of an adjacent shift register unit thereby enabling organizing the charge transfer device memory into a variety of configurations.

Claim 22

A charge transfer device memory configuration as set forth in claim 17 including means on said chip for selectively addressing a shift register unit from said plurality of units, and enabling entry of new data into said shift register and to said selected shift register unit or reading data stored therein.