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US4354245A Expired / Lapsed US ⏱️ 0.0 years remaining

Cyclic or periodic analog signal processing circuit

Assignee: Thales SA
•
Filing: 1980-08-06
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Granted: 1982-10-12
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Expires: 2000-08-06
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Abstract

Abstract This circuit makes it possible to produce in digital form position data corresponding to analog signals supplied by linvar transducers for processing by a digital computer. It comprises a multiplexer for successively transmitting the linvar signals to a processing circuit comprising, a comparator with a digital output for comparing the measuring signal of a transducer with the corresponding supply signal after the latter has been multiplied by an analog coefficient corresponding to a digital value stored in a memory relooped on itself across an adder-subtracter, which is controlled from the comparator output for agreeing the value V M /V R , to within an integration quantity.

Inventors

  • 👤 Francois E. Delegue

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 03:03
CPC Classifications
G; G06; G06J; G06J1/00; H; H03; H03M; H03M1/00; H03M1/10; H03M1/1009; H03M1/1033; H03M1/1038; H03M1/1047

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 201 words
A cyclic analog signal processing circuit, intended for processing signals from a plurality n of linvars, each linvar supplying an induced signal V Mi proportional to the displacement to be measured and to the reference signal V Ri supplying the transducer, said circuit comprising: multiplexer means for successively transmitting the analog signals of the transducers, supplying the induced signal V Mi by a first output and the reference signal of the corresponding transducer by a second output; a memory for successively storing the digital values V Mi /V Ri representative of the respective displacements of the transducers, said memory being relooped on itself across an adder-subtracter circuit; a multiplier for multiplying the reference signal V Ri of the second output by the corresponding value V M /V R extracted from the memory and being converted in analog form in a digital-analog conversion circuit; control means comprising a differential comparator with a digital output for comparing the output of the multiplier with the induced signal V Mi of the first output and for supplying a binary control signal; and a circuit for the incrementation and decrementation control of the adder-subtracter circuit as a function of the state of said binary control signal.
Claim 2
Dependent Claim 201 words
A cyclic analog signal processing circuit, intended for processing signals from a plurality n of linvars, each linvar supplying an induced signal V Mi proportional to the displacement to be measured and to the reference signal V Ri supplying the transducer, said circuit comprising: multiplexer means for successively transmitting the analog signals of the transducers, supplying the induced signal V Mi by a first output and the reference signal of the corresponding transducer by a second output; a memory for successively storing the digital values V Mi /V Ri representative of the respective displacements of the transducers, said memory being relooped on itself across an adder-subtracter circuit; a multiplier for multiplying the reference signal V Ri of the second output by the corresponding value V M /V R extracted from the memory and being converted in analog form in a digital-analog conversion circuit; control means comprising a differential comparator with a digital output for comparing the output of the multiplier with the induced signal V Mi of the first output and for supplying a binary control signal; and a circuit for the incrementation and decrementation control of the adder-subtracter circuit as a function of the state of said binary control signal.
Claim 3
Dependent Claim 49 words
A circuit according to claim 1, wherein said control means comprises a second comparator with a digital output receiving the reference signal and supplying the information of corresponding sign of said signal and an exclusive-OR circuit supplied by two comparators and supplying the binary incrementation-decrementation signal to the adder-subtracter.
Claim 4
Dependent Claim 50 words
A circuit according to claim 2, wherein said control means comprises means for validating the incrementation-decrementation control for an amplitude of the reference signal outside a given range +V 1 to -V 2 corresponding to the synchronous zero passages of the signals V Mi and V Ri to be processed.
Claim 5
Dependent Claim 66 words
A circuit according to claim 3, wherein the validation means incorporate the second comparator for comparing the reference signal with a positive voltage +V 1 , a third comparator with a digital output for comparing this signal with a negative voltage -V 2 and an OR circuit supplied by the outputs of the second and third comparators and supplying a corresponding validation signal to the adder-subtracter.
Claim 6
Dependent Claim 36 words
A circuit according to any one of claims 1 to 4, wherein the memory and adder-subtracter circuit form part of a microprocessor ensuring the timing of the successive memory sampling operations and which controls the multiplexer.
Claim 7
Dependent Claim 32 words
A circuit according to claim 4, wherein the memory and adder-subtracter circuit form part of a digital computer ensuring the timing of the successive memory sampling operations and which controls the multiplexer.
Claim 8
Dependent Claim 88 words
A circuit according to claim 4 or 6 applied to an electrical flight control system in which the transducers of the linvar type comprise a transducer providing a roll command, a transducer providing an air brake command and a plurality of recopying transducers, the latter being distributed over the respective surfaces to be controlled by means of servo-controls, said processing circuit and the digital computer processing on the basis of the roll and air brake commands, together with the recopying signals the commands of the surface servo-control means.

References Cited (Backward Citations)

US3449553A Cited
US3573794A Cited
US3558863A Cited
DE2318519A1 Cited
FR2346905A1 Cited
US4159524A Cited
US4270177A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-10-11 1986-04-12 1986-10-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-10-11 1990-04-12 1990-10-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-10-11 1994-04-12 1994-10-12 $7700.00 Window Closed / Lapsed

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