Integrated semiconductor device having insulated gate field effect transistors with a buried insulating film

Claim 2

An integrated semiconductor device comprising a semiconductor substrate of a first conductivity type, an insulating film formed on said substrate, said insulating film comprising a plurality of apertures each exposing a part of the surface of said substrate, a semiconductor layer formed selectively on said insulating film and on said exposed parts of said surface of said substrate, said semiconductor layer comprising an epitaxial layer where in contact with the exposed parts of said substrate and a polycrystal layer on said insulating film, said polycrystal layer comprising wiring portions, a plurality of active elements formed in said epitaxial layer within selected ones of said apertures, each of said elements comprising at least a first region of a second conductivity type opposite to said first conductivity type, and a second region of said second conductivity type formed in said substrate under said insulating film, said second region extending so as to selectively cross said wiring portions of said polycrystal layer so as to electrically connect said first regions of at least two of said active elements.

Claim 3

An integrated semiconductor device according to claim 1, selected ones of said active elements comprising an insulated gate field effect transistor.

Claim 4

An integrated semiconductor device according to claim 1, selected ones of said active elements each comprising within said epitaxial layer a third region of said first conductivity type to form a pn junction with said first region of the same active element.

Claim 5

The device of claim 3, selected ones of said active elements within corresponding ones of said apertures comprising two of said first regions of said second conductivity type.

Claim 6

The device of claim 3, at least selected ones of said third regions comprising a relatively low conductivity of said first conductivity type compared to the conductivity of said substrate.

Claim 7

The device of claim 3, selected ones of said first regions of said second conductivity type not being adjacent to any portion of said polycrystal layer.

Claim 8

An integrated semiconductor device comprising a semiconductor substrate of a first conductivity type, an insulating film formed on said substrate, said insulating film comprising a plurality of apertures each of which exposes a part of the surface of said substrate, a semiconductor layer formed selectively on said insulating film and on said exposed parts of said surface of said substrate, said semiconductor layer comprising an epitaxial layer on said exposed parts of said substrate and a polycrystal layer on said insulating film, said polycrystal layer comprising wiring portions, a plurality of insulated gate field effect transistors formed in said epitaxial layer within selected ones of said apertures, each of said transistors having source and drain regions of a second conductivity type opposite to said first conductivity type, said source and drain regions being adjacent to said insulating film, and a first region of said second conductivity type formed in said substrate under at least a portion of said insulating film so as to selectively cross said wiring portions of said polycrystal layer, said first region extending to electrically connect selected ones of said source and drain regions of said transistors.

Claim 9

An integrated semiconductor device comprising a semiconductor substrate of a first conductivity type, an insulating film formed on said substrate, said insulating film comprising a plurality of apertures each of which exposes a part of the surface of said substrate, a semiconductor layer formed selectively on said insulating film and on said exposed parts of said surface of said substrate, said semiconductor layer comprising an epitaxial layer on said exposed parts of said substrate and a polycrystal layer on said insulating film, said polycrystal layer comprising wiring portions, a plurality of insulated gate field effect transistors formed in said epitaxial layer within selected ones of said apertures, each of said transistors having source and drain regions of a second conductivity type opposite to said first conductivity type, said source and drain regions being adjacent to said insulating film, and a first region of said second conductivity type formed in said substrate under at least a portion of said insulating film so as to selectively cross said wiring portions of said polycrystal layer, said first region extending to electrically connect selected ones of said source and drain regions of said transistors.

Claim 10

An integrated semiconductor device according to claim 7 comprising means for electrically connecting at least one of said source and drain regions of selected ones of said transistors to said polycrystal layer on said insulating layer.

Claim 11

An integrated semiconductor device comprising a semiconductor substrate of a first conductivity type, an insulating film formed on said substrate, said insulating film comprising a plurality of apertures each of which exposes a part of the surface of said substrate, a semiconductor layer formed selectively on said insulating film and on said parts of said surface of said substrate, said semiconductor layer comprising an epitaxial layer on said substrate and a polycrystal layer on said insulating film, at least one insulated gate field effect transistor having source and drain regions of a second conductivity type opposite to said first conductivity type formed in said epitaxial layer within respective one(s) of said apertures, a first region of said second conductivity type formed selectively in said substrate under said insulating film, said first region extending selectively from at least one of said source and drain regions in at least one of said apertures to a position in said substrate adjacent to at least one other of said apertures, a metal wiring layer extending selectively over said semiconductor layer, and means for electrically connecting said metal wiring layer to said first region through at least one of said apertures, said means comprising a second region of said second conductivity type formed in said epitaxial layer within the respective one(s) of said apertures, said second region extending to said first region and forming an ohmic contact with said metal wiring layer.

Claim 12

An integrated semiconductor device comprising a semiconductor substrate of a first conductivity type, an insulating film formed on said substrate, said insulating film comprising a plurality of apertures each of which exposes a part of the surface of said substrate, a semiconductor layer formed selectively on said insulating film and on said parts of said surface of said substrate, said semiconductor layer comprising an epitaxial layer on said substrate and a polycrystal layer on said insulating film, at least one insulated gate field effect transistor having source and drain regions of a second conductivity type opposite to said first conductivity type formed in said epitaxial layer within respective one(s) of said apertures, a first region of said second conductivity type formed selectively in said substrate under said insulating film, said first region extending selectively from at least one of said source and drain regions in at least one of said apertures to a position in said substrate adjacent to at least one other of said apertures, a metal wiring layer extending selectively over said semiconductor layer, and means for electrically connecting said metal wiring layer to said first region through at least one of said apertures, said means comprising a second region of said second conductivity type formed in said epitaxial layer within the respective one(s) of said apertures, said second region extending to said first region and forming an ohmic contact with said metal wiring layer.

Claim 13

The device of claim 7 or 9, portions of said epitaxial layer corresponding to selected ones of said transistors each comprising a region of relatively low conductivity of said first type compared to the conductivity of said substrate.

Claim 14

An integrated semiconductor device comprising a semiconductor substrate of a first conductivity type, an insulating film formed on said substrate, said insulating film having a plurality of apertures each of which exposes a part of the surface of said substrate, a semiconductor layer selectively formed on said insulating film and said parts of said surface of said substrate, said semiconductor layer comprising an epitaxial layer within each of said apertures and a polycrystal layer on said insulating film, a plurality of insulated gate field effect transistors, each of said transistors having source and drain regions of a second conductivity type opposite to said first conductivity type within selected ones of said apertures, selected ones of said source and drain regions extending to said polycrystal layer on said insulating film, and other selected ones of said source and drain regions terminating within said epitaxial layer, and a first region of said second conductivity type formed selectively in said substrate under said insulating film, said first region extending to electrically connect selected ones of said source and drain regions of said transistors not terminating within said epitaxial layer.

Claim 15

An integrated semiconductor device comprising a semiconductor substrate of a first conductivity type, an insulating film formed on said substrate, said insulating film having a plurality of apertures each of which exposes a part of the surface of said substrate, a semiconductor layer selectively formed on said insulating film and said parts of said surface of said substrate, said semiconductor layer comprising an epitaxial layer within each of said apertures and a polycrystal layer on said insulating film, a plurality of insulated gate field effect transistors, each of said transistors having source and drain regions of a second conductivity type opposite to said first conductivity type within selected ones of said apertures, selected ones of said source and drain regions extending to said polycrystal layer on said insulating film, and other selected ones of said source and drain regions terminating within said epitaxial layer, and a first region of said second conductivity type formed selectively in said substrate under said insulating film, said first region extending to electrically connect selected ones of said source and drain regions of said transistors not terminating within said epitaxial layer.

Claim 16

The device of claim 11, comprising at least one channel stopper comprising at least one region of said substrate having said first conductivity type beneath portions of said insulating film for isolation between selected ones of said transistors.

Claim 17

The device of claim 11, said source and drain regions terminating within said epitaxial layer not being adjacent to said polycrystal layer and to said source and drain regions extending to said polycrystal layer.

Claim 18

The device of claim 11, the portions of said epitaxial layer surrounding each of said source and drain regions terminating within said epitaxial layer having a conductivity of said first type that is relatively lower than the conductivity of said second type of said source and drain regions extending to said polycrystal layer and of said first region.

Claim 19

An integrated semiconductor device comprising a semiconductor substrate comprising a first region of a first conductivity type and a second region of a second conductivity type opposite to said first conductivity type, an insulating film selectively formed on said substrate, said insulating film having a plurality of first and second apertures, each of said first apertures exposing a part of said first region, and each of said second apertures exposing a part of said second region, a semiconductor layer selectively formed on said insulating film and said first apertures, said semiconductor layer comprising an epitaxial layer within each of said first apertures and a polycrystal layer on said insulating layer, and said epitaxial layer comprising third regions of said first conductivity type within selected ones of said first apertures, a plurality of first insulated gate field effect transistors selectively formed in said first apertures, each said transistor being formed to have source and drain regions of said second conductivity type adjacent to a respective one of said third regions, and a plurality of second insulated gate field effect transistors, each of said second transistors being formed in one of said second apertures with source and drain regions of said first conductivity type, and said first region electrically connecting selected ones of said third regions in said first apertures.

Claim 20

An integrated semiconductor device comprising a semiconductor substrate comprising a first region of a first conductivity type and a second region of a second conductivity type opposite to said first conductivity type, an insulating film selectively formed on said substrate, said insulating film having a plurality of first and second apertures, each of said first apertures exposing a part of said first region, and each of said second apertures exposing a part of said second region, a semiconductor layer selectively formed on said insulating film and said first apertures, said semiconductor layer comprising an epitaxial layer within each of said first apertures and a polycrystal layer on said insulating layer, and said epitaxial layer comprising third regions of said first conductivity type within selected ones of said first apertures, a plurality of first insulated gate field effect transistors selectively formed in said first apertures, each said transistor being formed to have source and drain regions of said second conductivity type adjacent to a respective one of said third regions, and a plurality of second insulated gate field effect transistors, each of said second transistors being formed in one of said second apertures with source and drain regions of said first conductivity type, and said first region electrically connecting selected ones of said third regions in said first apertures.

Claim 21

An integrated semiconductor device according to claim 15 comprising at least one metal wiring layer selectively extending over said semiconductor layer and means for electrically connecting said metal wiring layer to said first region through at least one of said first apertures, said means comprising a fourth region of said first conductivity type formed in said epitaxial layer within the respective one(s) of said first apertures, each said fourth region extending to said first region forming an ohmic contact with said metal wiring layer.