Patent EP0479730B1 successfully refreshed from Google Patents.
Patent US4348759A successfully refreshed from Google Patents.
US4348759A
Expired / Lapsed
US
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Automatic testing of complex semiconductor components with test equipment having less channels than those required by the component under test
Assignee: International Business Machines Corp
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Filing: 1979-12-17
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Granted: 1982-09-07
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Expires: 1999-12-17
Abstract
Abstract A method and apparatus for testing large or very large scale integrated circuit packages is described. The testing equipment required for testing such packages is assumed to lack the number of channels necessary to connect one channel to each input/output of the unit under test. A computer program classifies all input terminals in a plurality of categories, each of which corresponds to particular circuit type and electric network configuration connected to that pin. A unique set of DC levels is defined prior to testing for each class of inputs. These levels are supplied by the tester channels, each of which drives a multitude of input pins that belong to the same category. The assignment of tester channels in the aforementioned arrangement is implemented by means of multiplexers that select for each pin the appropriate set of DC levels, and a memory buffer contained in the tester, with the DC test patterns stored wherein. The bit configuration of each pattern controls plural switching devices that deliver the appropriate DC levels to the terminals of the unit.
Inventors
- 👤 Henri D. Schnurmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:54
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31926
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
115 words
An apparatus for testing large or very large integrated circuit packages, said apparatus including: a stored program computer; a tester interconnected with said computer said tester including, a memory buffer having m binary outputs, n tester channels, a plurality of multiplexer circuits connected to said n tester channels, a plurality of tester probes for contacting input and output contacts of a unit under test (UUT), and a plurality of solid state switches interconnecting said memory buffer, said plurality of multiplexer circuits and said plurality of test probes; and, said apparatus being characterized by the ability to effectively test a unit under test having a greater number of inputs and outputs than said n tester channels.
Claim 2
Independent Claim
115 words
An apparatus for testing large or very large integrated circuit packages, said apparatus including: a stored program computer; a tester interconnected with said computer said tester including, a memory buffer having m binary outputs, n tester channels, a plurality of multiplexer circuits connected to said n tester channels, a plurality of tester probes for contacting input and output contacts of a unit under test (UUT), and a plurality of solid state switches interconnecting said memory buffer, said plurality of multiplexer circuits and said plurality of test probes; and, said apparatus being characterized by the ability to effectively test a unit under test having a greater number of inputs and outputs than said n tester channels.
Claim 3
Dependent Claim
90 words
A test system for testing integrated circuit devices having m Input/Output terminals, said system including: a program controlled computer; a tester having n test channels, where m is an integer greater than n; an m bit memory buffer; and computer controlled switching network means interconnecting said computer, said n test channels, said m bit memory buffer and a device under test having m Input/Output terminals; said test system being characterized in that said test system having only n test channels effectively tests a device under test having m Input/Output terminals.
Claim 4
Dependent Claim
90 words
A test system for testing integrated circuit devices having m Input/Output terminals, said system including: a program controlled computer; a tester having n test channels, where m is an integer greater than n; an m bit memory buffer; and computer controlled switching network means interconnecting said computer, said n test channels, said m bit memory buffer and a device under test having m Input/Output terminals; said test system being characterized in that said test system having only n test channels effectively tests a device under test having m Input/Output terminals.
Claim 5
Dependent Claim
29 words
A test system for testing integrated circuit devices, as recited in claim 2, wherein said computer controlled switching network means includes interconnected multiplexer means and solid-state switching circuit means.
Claim 6
Dependent Claim
96 words
In a computer controlled high speed electronic test system, an improved tester, said tester comprising: a memory buffer having a capacity of at least m bits; a plurality of solid state switches connected between said memory buffer and a device under test having m input/output terminals; a plurality of multiplex circuits connected to said solid state switches; n test channels connected to said plurality of multiplexer circuits, where m is an integer greater than n, whereby a device under test having m input/output terminals may be effectively tested by a tester having only n test channels.
Claim 7
Dependent Claim
96 words
In a computer controlled high speed electronic test system, an improved tester, said tester comprising: a memory buffer having a capacity of at least m bits; a plurality of solid state switches connected between said memory buffer and a device under test having m input/output terminals; a plurality of multiplex circuits connected to said solid state switches; n test channels connected to said plurality of multiplexer circuits, where m is an integer greater than n, whereby a device under test having m input/output terminals may be effectively tested by a tester having only n test channels.
Claim 8
Dependent Claim
83 words
In a computer controlled high speed electronic test system, an improved tester, as claimed in claim 4, wherein a computer utilizing a computer program classifies said input terminals of said m input/output terminals of said device under test into classes wherein each member of a class has like electrical requirements and each input of a class is connected via a certain one of said solid state switches and a certain one of said multiplexer circuits to a single one of said test channels.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-06 | 1986-03-08 | 1986-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-06 | 1990-03-08 | 1990-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-06 | 1994-03-08 | 1994-09-07 | $7700.00 | Window Closed / Lapsed |