Timing generator for use with multi-phase control rectifier systems

Claim 2

For use with a multi-phase rectifier system of the type including a plurality of selectively gateable semiconductive devices coupled between a multi-phase power source and a d.c. load and arranged to couple rectified D.C. voltage across the load, a timing generator for selectively gating appropriate semiconductive devices at appropriate power line phase angles so as to controllably vary the rectified voltage, the timing generator comprising: means for producing a first signal having unique values representative of respective power line phase angles; comparator means adapted to receive a command signal indicative of the ignition phase angle at which gating is desired and for comparing the first and command signal values; the comparator means undergoing a transition in output state when the two signals are substantially equal; sequence means having a plurality of sequentially occuring output states and being responsive to the comparator means transition to assume the sequentially next output state when gating occurs, the sequence means including first decoding means responsive to the output states to couple uniquely respective semi-conductive devices to a source of gating pulses in accordance with the ignition pattern associated with the multi-phase source.

Claim 3

The timing generator of claim 1 wherein said first signal producing means includes means for cyclically producing a first ramp-like signal in phase syncronization with the power source.

Claim 4

The timing generator of claim 2 wherein the comparator means is adapted to receive a command signal having a magnitude indicative of the phase angle at which gating is desired and which produces a trigger signal in response to the passing of the ramp through the magnitude.

Claim 5

The timing generator of claim 1 or 3 wherein the sequence means has a cyclical sequence of output states.

Claim 6

The timing generator of claim 2 or 3 including means for cyclically producing a second ramp-like signal which is offset in phase from the first ramp-like signal first means for selectively applying the second ramp-like signal to the comparator means instead of the first ramp-like signal during discontinuation in the latter signal.

Claim 7

The timing generator of claim 5 including second means for modifying the command signal in accordance with the magnitude of the second ramp-like signal at the ignition angle and for selectively applying the modified command signal to the comparator means when the second ramp-like signal is so applied.

Claim 8

The timing generator of claim 6 wherein the first and second means are responsive to certain of the output states of the sequencing means to apply the modified command signal and the second ramp-like signal during an offset phase range, the offset phase range commencing after the ignition of a semiconductive device which is not susceptible to gating during the discontinuity of the first ramp-like signal and terminating after the last susceptible semiconductor device in the ignition pattern has been gated.

Claim 9

The timing generator of claim 5 wherein the first ramp-like signal producing means produces a multi-bit digital signal and the second ramp-like signal producing means is operative to modify at least a portion of the bits.

Claim 10

The timing generator of claim 8 wherein the portion includes the three MSB's.

Claim 11

The timing generator of claim 9 wherein the relationship between the three MSB's and modified three MSB's is: B.sub.8 =Q.sub.8 B.sub.9 =Q.sub.9 ·(Q.sub.8 ⊕Q.sub.10) B.sub.10 =Q.sub.10 ·(Q.sub.8 ⊕Q.sub.9) where: Q 8 , Q 9 , Q 10 are respectively the 3rd MSB, 2nd MSB and MSB of the first ramp, B 8 , B 9 , B 10 are respectively the 3rd MSB, 2nd MSB and MSB of the second ramp, Q means "not Q" ⊕ means "exclusive or"

Claim 12

The timing generator of claim 1 including second decoding means responsive to the comparator means transition to modify the command signal, the modification being such that the value of the modified command signal is substantially the value of the first signal at 360°/2n (electrical) after the transition (where n is the number of power line phases); and means for applying the modified command signal as the command signal to the comparator means.

Claim 13

For use with a three-phase rectifier system of the type including a plurality of selectively gateable semiconductive devices coupled between a three-phase power source and a d.c. load and arranged to couple rectified D.C. voltage across the load, a timing generator for selectively gating appropriate semiconductive devices at appropriate power line phase angles so as to controllably vary the rectified voltage, the timing generator comprising: means for cyclically producing a first multi-bit digital ramp-like signal of incrementally changing magnitude, means for syncronizing the ramp-like signal with a reference line voltage of the three-phase source so that the ramp-like signal exhibits unique values respectively representative of power source phase angles; comparator means adapted to receive a command signal indicative of the ignition phase angle at which gating is desired for undergoing a transition in output state when the first ramp-like signal passes through the command signal magnitude; sequence means having six sequentially occurring output states and being responsive to each transition to assume the sequentially next output state; first decoding means responsive to the output states of the sequence means to couple respective semiconductive devices to a source of gating pulses in accordance with the ignition pattern associated with the three-phase source; and second decoding means responsive to the output state of the sequence means to selectively modify the command signal and apply the modified command signal to the comparator means as the command signal, the modification being such as to define a new transition point 60° (electrical) after the last termination.

Claim 14

For use with a three-phase rectifier system of the type including a plurality of selectively gateable semiconductive devices coupled between a three-phase power source and a d.c. load and arranged to couple rectified D.C. voltage across the load, a timing generator for selectively gating appropriate semiconductive devices at appropriate power line phase angles so as to controllably vary the rectified voltage, the timing generator comprising: means for cyclically producing a first multi-bit digital ramp-like signal of incrementally changing magnitude, means for syncronizing the ramp-like signal with a reference line voltage of the three-phase source so that the ramp-like signal exhibits unique values respectively representative of power source phase angles; comparator means adapted to receive a command signal indicative of the ignition phase angle at which gating is desired for undergoing a transition in output state when the first ramp-like signal passes through the command signal magnitude; sequence means having six sequentially occurring output states and being responsive to each transition to assume the sequentially next output state; first decoding means responsive to the output states of the sequence means to couple respective semiconductive devices to a source of gating pulses in accordance with the ignition pattern associated with the three-phase source; and second decoding means responsive to the output state of the sequence means to selectively modify the command signal and apply the modified command signal to the comparator means as the command signal, the modification being such as to define a new transition point 60° (electrical) after the last termination.

Claim 15

The timing generator of claim 12 including means for producing a second ramp-like signal which offsets from the first ramp-like signal by 180° (electrical). the second decoder means being responsive to the output state of the sequencing means to selectively apply the second ramp-like signal to the comparator means for the range of power source phase angles during which the gating of semiconductive device might coincide with resetting of the first ramp-like signal; the second decoder means being operable to define a three-step offset cycle wherein the command signal is sequentially unmodified to define an initial transition point, modified to define a new transition point 60° (electrical) subsequent, and modified to define a third transition point 120° (electrical) subsequent to the initial transition point, the offset cycle being repeated when the comparator means is selectively coupled to either of the two ramp-like signals.