Buffer circuit

Claim 2

A buffer circuit for producing output signals of opposite phase relative to applied input signals, said buffer circuit comprising an input node; a first power source having a high potential; a second power source having a low potential; means for supplying said input node with input signals which change between high and low potential levels; a first inverter circuit including a series circuit of a load element and an input transistor, said input transistor being connected to said input node so as to perform a switching operation in response to said input signal to produce output signals of opposite phase to said input signals, said output signals being derived from an intermediate junction between said load element and said input transistor, the level of each output signal being changed opposite to each corresponding change of input signal level; a first transistor connected between said first power source and said input node; a second transistor connected between said second power source and said input node; means for connecting a gate of said first transistor to said intermediate junction; and a second inverter having an input terminal coupled to a gate of said intermediate junction and an output terminal connected to said second transistor, said first transistor being made conductive when said input signals change from a high to a low potential level and said output signal changes from a low to a high potential level thereby to shift the level of the potential at said input node toward that of said first power source without changing the phase of the level at said input node and said second transistor being made conductive when said input signals change from a low to a high potential level and said output signal changes from a high to a low potential level thereby to shift the level of the potential at said input node toward that of said second power source without changing the phase of the level of said input node.

Claim 3

The circuit according to claim 1, in which the ratio of the channel width to channel length of said input transistor is larger than those of said first and second transistors.

Claim 4

A sense circuit comprising a sense node to which an information signal stored in a selected memory cell is applied; a first power source having a high potential; a second power source having a low potential; said information signal being changeable between a first logic state of high potential level and a second logic state of low potential level; a first inverter circuit having an input terminal connected to said sense node and having an output terminal; said first inverter circuit including a load element and an input transistor connected in series between said first power source and said second power source; said input transistor being switched in response to a change in logic state potential level at said sense node thereby to produce an output signal of opposite logic state potential level to that of said sense node; a first control transistor connected between said first power source and said sense node; a second control transistor connected between said second power source and said sense node; means for connecting a control terminal of said first control transistor with said output terminal of said first inverter circuit; and a second inverter circuit having an input terminal receiving output signals from said first inverter circuit; means for supplying a control terminal of said second control transistor with output signals from said second inverter circuit, said first control transistor being made conductive when the output signal of said first inverter circuit is in said first logic state thereby to shift the potential level at said sense node in a direction towards the potential level of said first power source without changing the logic state at said sense node from said second logic state to the first logic state, said second control transistor being made conductive when the output signal of said first inverter circuit is in said second logic state thereby to shift the potential level at said sense node in a direction towards the potential level of said second power source without changing the logic state at said sense node from the first logic state to the second logic state, whereby the amplitude of the potential of said information signal at said sense node is made small.

Claim 5

A sense circuit comprising a sense node to which an information signal stored in a selected memory cell is applied; a first power source having a high potential; a second power source having a low potential; said information signal being changeable between a first logic state of high potential level and a second logic state of low potential level; a first inverter circuit having an input terminal connected to said sense node and having an output terminal; said first inverter circuit including a load element and an input transistor connected in series between said first power source and said second power source; said input transistor being switched in response to a change in logic state potential level at said sense node thereby to produce an output signal of opposite logic state potential level to that of said sense node; a first control transistor connected between said first power source and said sense node; a second control transistor connected between said second power source and said sense node; means for connecting a control terminal of said first control transistor with said output terminal of said first inverter circuit; and a second inverter circuit having an input terminal receiving output signals from said first inverter circuit; means for supplying a control terminal of said second control transistor with output signals from said second inverter circuit, said first control transistor being made conductive when the output signal of said first inverter circuit is in said first logic state thereby to shift the potential level at said sense node in a direction towards the potential level of said first power source without changing the logic state at said sense node from said second logic state to the first logic state, said second control transistor being made conductive when the output signal of said first inverter circuit is in said second logic state thereby to shift the potential level at said sense node in a direction towards the potential level of said second power source without changing the logic state at said sense node from the first logic state to the second logic state, whereby the amplitude of the potential of said information signal at said sense node is made small.

Claim 6

The circuit according to claim 1 or 3, in which said load element is composed of a depletion type field effect transistor.

Claim 7

The circuit according to claim 3, in which the ratio of the channel width to channel length of said first control transistor is the same as that of said second control transistor.

Claim 8

The circuit according to claim 3, in which the ratio of the channel width to channel length of said input transistor is larger than those of said first and second control transistors.

Claim 9

The circuit according to claim 3, further comprising a plurality of memory cells, and a plurality of transfer gates coupling said plurality of memory cells, respectively, to said sense node.

Claim 10

A buffer circuit comprising an input node; an output node; a first power source; a second power source; a first enhancement type field effect transistor having its drain connected to said output node, its gate connected to said input node, and its source connected to said second power source; a first depletion type field effect transistor having its drain connected to said first power source, its gate connected to said output node and its source connected to said output node; a second enhancement type field effect transistor having its gate connected to said output node, its source connected to said second power source and having a drain; a second depletion type field effect transistor having its drain connected to said first power source and having its gate and source commonly connected to the drain of said second enhancement type field effect transistor; a third enhancement type field effect transistor having its drain connected to said first power source, its gate connected to said output node, and its source connected to said input node; and a fourth enhancement type field effect transistor having its drain connected to said input node, its gate connected to the drain of said second enhancement type transistor and its source connected to said second power source.

Claim 11

A buffer circuit comprising an input node; an output node; a first power source; a second power source; a first enhancement type field effect transistor having its drain connected to said output node, its gate connected to said input node, and its source connected to said second power source; a first depletion type field effect transistor having its drain connected to said first power source, its gate connected to said output node and its source connected to said output node; a second enhancement type field effect transistor having its gate connected to said output node, its source connected to said second power source and having a drain; a second depletion type field effect transistor having its drain connected to said first power source and having its gate and source commonly connected to the drain of said second enhancement type field effect transistor; a third enhancement type field effect transistor having its drain connected to said first power source, its gate connected to said output node, and its source connected to said input node; and a fourth enhancement type field effect transistor having its drain connected to said input node, its gate connected to the drain of said second enhancement type transistor and its source connected to said second power source.