Floating hybrid switch

Claim 2

A floating hybrid switching circuit comprising a VMOS transistor having a source drain path and a gate electrode, a pair of complementary series connected bipolar transistors having common base input electrodes and common output electrodes, the common output electrodes having the same nomenclature and being d.c. coupled to the gate electrode, said series transistors having a main current path between a power supply terminal and a floating reference terminal, said reference terminal being d.c. connected to one electrode of the field effect transistor source drain path and one electrode of the main path of the series transistors to maintain said one electrode at the same floating d.c. reference potential, a control circuit for deriving an output signal coupled to the common base electrodes, said output signal having first and second levels respectively causing a main current path of a first of the bipolar transistors to be cut off while a main current path of the second bipolar transistor is conducting and the main current path of the first bipolar transistor to be conducting while the main current path of the second bipolar transistor is cut off, the bipolar transistors when responsive to the first level maintaining the gate electrode at a predetermined constant voltage relative to the reference terminal via a low impedance path between the reference terminal and the gate electrode to cut off the VMOS transistor source drain path and when responsive to the second level coupling the voltage at the other electrode of the bipolar transistor main current path to the gate electrode to activate the VMOS transistor source drain path into a conducting state, and diode means connected between the reference terminal and the other electrode of the main current path of the bipolar transistors for maintaining a constant predetermined voltage difference between the reference terminal and the other electrode of the main current path of the bipolar transistors to prevent false triggering of the bipolar transistors in response to transient voltage variations between the power supply and reference terminals.

Claim 3

The circuit of claim 1 wherein the voltage at the reference terminal is susceptible to variations below a nominal voltage therefor, the control circuit including d.c. circuit means between the floating reference terminal and the common base electrodes for maintaining a constant voltage difference equal to the first voltage level and a low impedance between the floating reference terminal and the common base electrodes in response to the reference terminal having the negative variations while the control circuit derives the first voltage level, the control circuit providing a high impedance between the floating reference terminal and the common base electrodes while the control circuit derives the second voltage level.

Claim 4

The circuit of claim 1 wherein the voltage at the reference terminal is susceptible to variations above a nominal voltage therefor, further including a diode shunting the source drain path and polarized to pass current from the reference terminal in an opposite direction from the source drain path for bypassing the source drain path in response to the reference terminal having the positive variations while the control circuit derives the first voltage level, the control circuit providing a high impedance between the floating reference terminal and the common base electrodes while the control circuit derives the second voltage level.

Claim 5

A floating hybrid switching circuit comprising a VMOS transistor having a source drain path and a gate electrode, a pair of complementary series connected bipolar transistors having common base input electrodes and common output electrodes, the common output electrodes having the same nomenclature and being d.c. coupled to the gate electrode, said series transistors having a main current path between a power supply terminal and a floating reference terminal, said reference terminal being d.c. connected to one electrode of the field effect transistor source drain path and one electrode of the main path of the series transistors to maintain said one electrode at the same floating d.c. reference potential, a control circuit for deriving an output signal coupled to the common base electrodes, said output signal having first and second levels respectively causing a main current path of a first of the bipolar transistors to be cut off while a main current path of the second bipolar transistor is conducting and the main current path of the first bipolar transistor to be conducting while the main current path of the second bipolar transistor is cut off, the bipolar transistors when responsive to the first level maintaining the gate electrode at a predetermined constant voltage relative to the reference terminal via a low impedance path between the reference terminal and the gate electrode to cut off the VMOS transistor source drain path and when responsive to the second level coupling a forward biasing voltage to the gate electrode to activate the VMOS transistor source drain path into a conducting state, the voltage at the reference terminal being susceptible to variations below a nominal voltage therefor, the control circuit including d.c. circuit means between the floating reference terminal and the common base electrodes for maintaining a constant voltage difference equal to the first voltage level and a low impedance between the floating reference terminal and the common base electrodes in response to the reference terminal having the negative variations while the control circuit derives the first voltage level, the control circuit providing a high impedance between the floating reference terminal and the common base electrodes while the control circuit derives the second voltage level.

Claim 6

A floating hybrid switching circuit comprising a VMOS transistor having a source drain path and a gate electrode, a pair of complementary series connected bipolar transistors having common base input electrodes and common output electrodes, the common output electrodes having the same nomenclature and being d.c. coupled to the gate electrode, said series transistors having a main current path between a power supply terminal and a floating reference terminal, said reference terminal being d.c. connected to one electrode of the field effect transistor source drain path and one electrode of the main path of the series transistors to maintain said one electrode at the same floating d.c. reference potential, a control circuit for deriving an output signal coupled to the common base electrodes, said output signal having first and second levels respectively causing a main current path of a first of the bipolar transistors to be cut off while a main current path of the second bipolar transistor is conducting and the main current path of the first bipolar transistor to be conducting while the main current path of the second bipolar transistor is cut off, the bipolar transistors when responsive to the first level maintaining the gate electrode at a predetermined constant voltage relative to the reference terminal via a low impedance path between the reference terminal and the gate electrode to cut off the VMOS transistor source drain path and when responsive to the second level coupling a forward biasing voltage to the gate electrode to activate the VMOS transistor source drain path into a conducting state, the voltage at the reference terminal being susceptible to variations below a nominal voltage therefor, the control circuit including d.c. circuit means between the floating reference terminal and the common base electrodes for maintaining a constant voltage difference equal to the first voltage level and a low impedance between the floating reference terminal and the common base electrodes in response to the reference terminal having the negative variations while the control circuit derives the first voltage level, the control circuit providing a high impedance between the floating reference terminal and the common base electrodes while the control circuit derives the second voltage level.

Claim 7

The circuit of claim 4 wherein the voltage at the reference terminal is susceptible to variations above a nominal voltage therefor, further including a diode shunting the source drain path and polarized to pass current from the reference terminal in an opposite direction from the source drain path for bypassing the source drain path in response to the reference terminal having the positive variations while the control circuit derives the first voltage level, the control circuit providing a high impedance between the floating reference terminal and the common base electrodes while the control circuit derives the second voltage level.

Claim 8

The circuit of claim 2, 4 or 5 wherein the control circuit includes a pair of complementary inverting field effect transistors having: series connected source drain paths connected to d.c. shunt the main current path of the bipolar transistors, common gate electrodes responsive to a bilevel signal and common output electrodes between the series connected source drain paths, the common output electrodes being d.c. coupled to the common base electrodes.

Claim 9

The circuit of claim 2, 4 or 5 wherein the control circuit includes first and second pairs of complementary inverting field effect transistors, the first pair of transistors being cascaded with the second pair of transistors by a d.c. circuit, each of the pair of transistors having series connected source drain paths connected to d.c. shunt the main current path of the bipolar transistors, common gate electrodes responsive to a bilevel signal and common output electrodes between the series connected source drain paths, the common output electrodes of the first pair being d.c. coupled to the common gate electrodes of the second pair, the common output electrodes of the second pair being d.c. coupled to the common base electrodes.

Claim 10

The circuit of claim 7 wherein the control circuit includes a bypass network connected between the first and second pairs of complementary inverting field effect transistors for shunting transient input signals coupled to the first pair of inverting complementary field effect transistors from an input of the second pair of inverting complementary field effect transistors to said floating reference terminal.

Claim 11

The circuit of claim 2 wherein the voltage at the reference terminal is susceptible to variations above a nominal voltage therefor, further including a diode shunting the source drain path and polarized to pass current from the reference terminal in an opposite direction from the source drain path for bypassing the source drain path in response to the reference terminal having the positive variations while the control circuit derives the first voltage level.