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US3798466A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuits including combined field effect and bipolar transistors

Assignee: AT&T Inc
•
Filing: 1972-03-22
•
Granted: 1974-03-19
•
Expires: 1992-03-22
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Abstract

Abstract The output signal of a BIGFET is increased by connecting an auxiliary IGFET between the bias source and the output. The gate of the auxiliary IGFET is actuated by the input signal. Current through the BIGFET is periodically controlled to permit voltage ''''pull-up'''' by the auxiliary IGFET.

Inventors

  • 👤 G Cheney

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 21:56
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/096

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 192 words
In a BIGFET circuit of the type comprising a first IGFET device having source, gate and drain regions, a bipolar transistor having emitter, collector and base regions, means comprising a bias source connected to the bipolar transistor collector region for biasing the bipolar transistor, the first IGFET drain region being connected to the bipolar base region, means for applying an input digital signal to the first IGFET gate region, and means for deriving an output digital signal from the bipolar emitter region, the improvement comprising: a second IGFET device having a gate region connected, by way of a completely passive transmission line, to the gate of the first IGFET, a source region connected to the bipolar transistor collector region, and a drain region connected to the emitter of the bipolar transistor; and means for periodically changing the emitter load impedance of the bipolar transistor and for periodically altering the current path through the bipolar transistor comprising a third IGFET device having a source region connected to the drain region of the second IGFET device, a drain region connected to a reference potential, and a gate region connected to a periodic switching means.
Claim 2
Dependent Claim 192 words
In a BIGFET circuit of the type comprising a first IGFET device having source, gate and drain regions, a bipolar transistor having emitter, collector and base regions, means comprising a bias source connected to the bipolar transistor collector region for biasing the bipolar transistor, the first IGFET drain region being connected to the bipolar base region, means for applying an input digital signal to the first IGFET gate region, and means for deriving an output digital signal from the bipolar emitter region, the improvement comprising: a second IGFET device having a gate region connected, by way of a completely passive transmission line, to the gate of the first IGFET, a source region connected to the bipolar transistor collector region, and a drain region connected to the emitter of the bipolar transistor; and means for periodically changing the emitter load impedance of the bipolar transistor and for periodically altering the current path through the bipolar transistor comprising a third IGFET device having a source region connected to the drain region of the second IGFET device, a drain region connected to a reference potential, and a gate region connected to a periodic switching means.
Claim 3
Dependent Claim 37 words
The improvement of claim 1 further comprising: an output capacitance Cout associated with the output of the BIGFET circuit; and wherein the third IGFET device comprises means for periodically discharging the capacitance Cout to a reference potential.
Claim 4
Dependent Claim 40 words
The improvement of claim 2 wherein: the BIGFET output is coupled to a load having an input capacitance Cin; and further comprising a fourth IGFET for periodically altering the potential across capacitance Cin by transmitting charge between Cout and Cin.
Claim 5
Dependent Claim 35 words
The improvement of claim 3 wherein: the third IGFET and fourth and IGFET devices are actuated by first and second clock sources having a pulse output of the same frequency but of a different phase.
Claim 6
Dependent Claim 31 words
The improvement of claim 4 wherein: an input of the BIGFET is connected to a logic circuit; and said first and second clock sources constitute clock sources for said logic circuit.
Claim 7
Dependent Claim 21 words
The improvement of claim 5 wherein: the first and second clock sources generate pulsed outputs that are substantially 180 degress out-of-phase.
Claim 8
Dependent Claim 13 words
The improvement of claim 5 wherein: the logic circuit is a shift register.

References Cited (Backward Citations)

US3636372A Cited
US3586989A Cited
US3553541A Cited
US3582975A Cited
US3601628A Cited
US3601630A Cited
US3649843A Cited
US3631528A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-03-18 1977-09-17 1978-03-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-03-18 1981-09-17 1982-03-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-03-18 1985-09-17 1986-03-19 $7700.00 Window Closed / Lapsed

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