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US4347403A Expired / Lapsed US ⏱️ 0.0 years remaining

Electrical waveform synthesizer

Assignee: United States Department of the Navy
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Filing: 1980-04-24
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Granted: 1982-08-31
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Expires: 2000-04-24
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Abstract

Abstract This electrical waveform synthesizer uses a digital feedback loop circuit which includes selectable inputs for multiplex or recirculation operation, and a shift register whose shift rate is controlled by an adjustable precision clock so as to accurately adjust the frequency of the output waveform. The adjustable clock features a precision oscillator whose pulse rate is divided by a selectable-logic rate-divider circuit.

Inventors

  • 👤 Joseph E. Schwager
  • 👤 Harry E. Urban

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 16:22
CPC Classifications
G; G04; G04F; G04F5/00; G04F5/02; G04F5/025; G10; G10H; G10H7/00; G10H7/02; G10H7/04; G10H7/045

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 233 words
An electrical waveform synthesizer comprising: multiplex and recirculate means having a data input, a load/circulate input, and a recirculated signal input for receiving a digital input signal; a shift register connected to said multiplex and recirculate means for receipt of digital output signals therefrom and having a plurality of loadable stages for loading digital signals therein, a clock input where clock signals maybe applied to effect shifting of data between said plurality of loadable stages, and an output which is connected to said recirculated signal input of said multiplex and recirculate means; a digital-to-analog converter connected to said output of said shift register; and clock means connected to the clock input of said shift register said clock means including a plurality of frequency division circuits, each frequency division circuit further including; an input register for receiving control signals; an adder circuit connected to said input register for receipt of augend signals therefrom, an output register connected to said adder circuit to receive signals therefrom and connected to said adder circuit to provided addend signals therefor and an output connected to adder circuits of succeeding frequency circuits, if any, for providing additional addend signals therefor, the adder circuit of one of said frequency circuits having an output connected to said shift register clock input, and an oscillator having an output connected to each of said output registers of said plurality of frequency division circuits.
Claim 2
Dependent Claim 233 words
An electrical waveform synthesizer comprising: multiplex and recirculate means having a data input, a load/circulate input, and a recirculated signal input for receiving a digital input signal; a shift register connected to said multiplex and recirculate means for receipt of digital output signals therefrom and having a plurality of loadable stages for loading digital signals therein, a clock input where clock signals maybe applied to effect shifting of data between said plurality of loadable stages, and an output which is connected to said recirculated signal input of said multiplex and recirculate means; a digital-to-analog converter connected to said output of said shift register; and clock means connected to the clock input of said shift register said clock means including a plurality of frequency division circuits, each frequency division circuit further including; an input register for receiving control signals; an adder circuit connected to said input register for receipt of augend signals therefrom, an output register connected to said adder circuit to receive signals therefrom and connected to said adder circuit to provided addend signals therefor and an output connected to adder circuits of succeeding frequency circuits, if any, for providing additional addend signals therefor, the adder circuit of one of said frequency circuits having an output connected to said shift register clock input, and an oscillator having an output connected to each of said output registers of said plurality of frequency division circuits.
Claim 3
Dependent Claim 20 words
The synthesizer of claim 1 further comprising a low pass filter for providing a filtered output of the analog waveform.
Claim 4
Dependent Claim 22 words
The synthesizer of claim 1 wherein the shift register output is recirculatable at a rate sufficient to provide desired output waveform frequencies.
Claim 5
Dependent Claim 25 words
The synthesizer of claim 2 wherein the cut-off high frequency of the low pass filter is proximally above the highest output frequency of the converter.
Claim 6
Dependent Claim 14 words
The synthesizer of claim 4 wherein the cut-off frequency of the filter is controllable.
Claim 7
Dependent Claim 22 words
The synthesizer of claim 1 wherein the number of digital segments of the waveform varies inversely with the frequency of the waveform.
Claim 8
Dependent Claim 39 words
The synthesizer of claim 1 wherein the respective stages are loadable with different values by the logic means at a rate related to the clock frequency and the means for recirculating is inhibitable upon command from the logic means.
Claim 9
Dependent Claim 27 words
An electrical waveform synthesizer according to claim 1 in which said multiplex and recirculate means inhibits recirculation upon a predetermined signal being applied to said load/circulate input.
Claim 10
Dependent Claim 37 words
An electrical waveform synthesizer according to claim 1 wherein said output register of said frequency divider circuit is configured to feed the value stored therein to said adder only when the oscillator is of a predetermined polarity.

References Cited (Backward Citations)

US3500213A Cited
US3577084A Cited
US3777278A Cited
US4124898A Cited
US4244262A Cited
US4228713A Cited
US4223583A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-08-30 1986-03-01 1986-08-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-08-30 1990-03-01 1990-08-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-08-30 1994-03-01 1994-08-31 $7700.00 Window Closed / Lapsed

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