US4124898A
Expired / Lapsed
US
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Programmable clock
Assignee: Nortel Networks Ltd
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Filing: 1977-06-10
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Granted: 1978-11-07
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Expires: 1997-06-10
Abstract
Abstract A clock signal generator is responsive to a signal having a pulse repetition rate, and to a word instruction to generate a new signal having a pulse repetition rate according to the word instruction. The clock signal generator in one embodiment is capable of providing a plurality of clock signals each according to an associated word instruction.
Inventors
- 👤 Ernst A. Munter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:56
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/457; G; G06; G06F; G06F1/00; G06F1/04; G06F1/08
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
196 words
A clock circuit for generating a plurality of clock signals corresponding to a plurality of associated instruction words and a master clock signal having a predetermined pulse repetition frequency, the clock circuit comprising: adder means having first inputs for sequentially receiving the plurality of associated instruction words, n second inputs and n outputs; n shift registers, each connected between one of the n outputs and an associated one of the n second inputs, each shift register having a plurality of stages and each shift register being responsive to the master clock signal to shift bits therethrough, one of the shift registers being connected between the most significant output and the most significant second input of the adder means, said shift register being the most significant shift register; an output register having inputs connected to each of the stages of the most significant shift register, the output register being responsive to a second clock signal occurring at a rate of the pulse repetition frequency of the master clock signal divided by the number of stages in the most significant shift register; whereby a plurality of clock signals corresponding to the plurality of associated instruction words is generated.
Claim 2
Dependent Claim
196 words
A clock circuit for generating a plurality of clock signals corresponding to a plurality of associated instruction words and a master clock signal having a predetermined pulse repetition frequency, the clock circuit comprising: adder means having first inputs for sequentially receiving the plurality of associated instruction words, n second inputs and n outputs; n shift registers, each connected between one of the n outputs and an associated one of the n second inputs, each shift register having a plurality of stages and each shift register being responsive to the master clock signal to shift bits therethrough, one of the shift registers being connected between the most significant output and the most significant second input of the adder means, said shift register being the most significant shift register; an output register having inputs connected to each of the stages of the most significant shift register, the output register being responsive to a second clock signal occurring at a rate of the pulse repetition frequency of the master clock signal divided by the number of stages in the most significant shift register; whereby a plurality of clock signals corresponding to the plurality of associated instruction words is generated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-06 | 1982-05-08 | 1982-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-06 | 1986-05-08 | 1986-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-06 | 1990-05-08 | 1990-11-07 | $7700.00 | Window Closed / Lapsed |