US3824385A
Expired / Lapsed
US
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Digital divider circuit
Assignee: Robert Bosch GmbH
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Filing: 1973-10-10
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Granted: 1974-07-16
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Expires: 1993-10-10
Abstract
Abstract The frequency of an input pulse train serves as the dividend and operates a first counter in continuously repeated cycles. The divisor is stored as a binary number in a divisor register and, by means of an adder, the divisor and successive integral multiples thereof are successively registered in a summing register at intervals determined by the operation of a comparator which compares the more significant digits of the summing register with all of the lower integral multiple of the divisor, the adder or the summing register is advanced to present the next higher multiple. The succession of output pulses of the comparator provide a pulse train the frequency of which is the quotient. The divisor may be generated by a pulse train and periodically registered, either as a number proportional to the period of the pulse train or a number proportional to the frequency of the pulse train. The divisor register, adder and summing register have additional places for less significant bits in excess of the number of places in the first counter, enabling great reduction in the maximum rounding error.
Inventors
- 👤 U Kiencke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:07
CPC Classifications
G; G06; G06J; G06J1/00; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/481; G01P3/489; G06F; G06F7/00; G06F7/60; G06F7/62
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
177 words
A digital division circuit suitable for speed measurements in motor vehicles, comprising: first register means (Y) for storing the divisor as a binary number; binary adder means (A) having a first set of inputs connected to the outputs of said first register means (Y); second register means (S) having its inputs connected to the outputs of said adder means (A) and its outputs connected to a second set of inputs of said adder means (A); first counting means (X) responsive to an input pulse train the frequency (fx) of which constitutes the dividend quantity; comparator means (v) for comparing the outputs of said first counting means (X) and the outputs of said second register means (S) and arranged to enable the advance of said second register means (S) to register the output of said adder means (A) only when a match of the outputs of said first counting means (X) and of said second register means (S) is found, and arranged also to provide an output pulse at each such match to form the quotient frequency (fv).
Claim 2
Dependent Claim
177 words
A digital division circuit suitable for speed measurements in motor vehicles, comprising: first register means (Y) for storing the divisor as a binary number; binary adder means (A) having a first set of inputs connected to the outputs of said first register means (Y); second register means (S) having its inputs connected to the outputs of said adder means (A) and its outputs connected to a second set of inputs of said adder means (A); first counting means (X) responsive to an input pulse train the frequency (fx) of which constitutes the dividend quantity; comparator means (v) for comparing the outputs of said first counting means (X) and the outputs of said second register means (S) and arranged to enable the advance of said second register means (S) to register the output of said adder means (A) only when a match of the outputs of said first counting means (X) and of said second register means (S) is found, and arranged also to provide an output pulse at each such match to form the quotient frequency (fv).
Claim 3
Dependent Claim
69 words
A division circuit as defined in claim 1 in which said first register means (Y), said adder means (A) and said second register means (S) each have a number of additional places (Y1 to Y4, A1 to A4 and S1 to S4) in excess of the number of places possessed by said comparator (V), which additional places are assigned to the less significant bits of said divisor binary number.
Claim 4
Dependent Claim
49 words
A division circuit as defined in claim 1 in which said adder means (A) is provided with a supplementary input (10) arranged for enabling the addition function of said adder means (A), and in which said supplementary input (10) is connected with the output (11) of said comparator (V).
Claim 5
Dependent Claim
48 words
A division circuit as defined in claim 3 in which a first loading gate (U) is provided having individual stages (U1 to U9) interposed between the corresponding stages (Y1 to Y9) of said first register means (Y) and said first set of inputs of said adder means (A).
Claim 6
Dependent Claim
66 words
A division circuit as defined in claim 4 in which the individual stages (U1 to U9) of said first loading gate (U) each consist of an AND-gate having a first input connected to the corresponding stage (Y1 to Y9), having a second input connected to the output (11) of said comparator (V) and having its output connected to the corresponding input of said adder means (A).
Claim 7
Dependent Claim
66 words
A division circuit as defined in claim 3 in which said supplementary input (10) of said adder means (A) comprises an AND-gate (U11) having a first input connected to the output (11) of said comparator (C), its output connected to a timing pulse input (T) of said second register means (S) and a second input connected to connector means for applying a basic pulse frequency (fO).
Claim 8
Dependent Claim
82 words
A division circuit as defined in claim 1 in which said divisor is supplied to said first register means (Y) as a binary number by a second counting means (Z) responsive to a second input pulse train the frequency (fy) of which constitutes the divisor quantity, said second counting means being provided with means for loading the bit content of said second counting means at regular intervals into said first register means (Y) and immediately thereafter resetting said second counting means (Z).
Claim 9
Dependent Claim
34 words
A division circuit as defined in claim 7 in which a second loading gate (W) is provided for loading the bit content of said second counting means (Z) into said first register means (Y).
Claim 10
Dependent Claim
89 words
A division circuit as defined in claim 8 in which logic circuit means are provided responsive to said second input pulse train (fy) for activating the load control input (18) of said second loading gate (W), said logic ciRcuit comprising: a sequence of two countdown flipflop (13, 15) responsive to pulses of said second input pulse train, and an AND-gate responsive to outputs of each of said flipflops of respectively opposite polarity and having its output connected to said loading control input (18) of said second loading gate (W).
Claim 11
Dependent Claim
50 words
A division circuit as defined in claim 9 in which a third countdown flipflop (17) is provided with its input connected to the output of said AND-gate (16) of said logic circuit means and with an output (Q1) connected with a reset input (R) of said second counting means (Z).
Claim 12
Dependent Claim
73 words
A division circuit as defined in claim 8 in which the individual stages (Y1 to Y9) of said first register means (Y) are constituted as JK flipflop means (23) and in which each stage (W1 to W9) of said second loading gate (w) comprises two AND-gates (22, 25) having their respective outputs connected to the two inputs (JK) of said JK flipflop means (23) of the corresponding stage of said first register means.
Claim 13
Dependent Claim
117 words
A division circuit as defined in claim 11 in which said AND-gates (22, 25) of said first register means each have an input (18) functioning as said loading control input connected to the output of said AND-gate (16) of said logic circuit means and in which the second input of a first AND-gate (22) of said two AND-gates is connected directly to the output (21) of the corresponding stage (Z1 . . .) of said second counting stage (Z) and the second input of said second AND-gate (25) of said two AND-gates is connected over an inverting stage (24) to said output (21) of said corresponding stage (Z1 . . .) of said second counting means (Z).
Claim 14
Independent Claim
318 words
A method of measuring the ratio or product of the speeds of two rotating members with one speed specified as dividend and the other as divisor, comprising the steps of: generating pulse trains of frequencies respectively proportioned to the speeds of said rotating members; driving a first binary counter of a first predetermined number of places with the dividend frequency; driving a second binary counter of a second predetermined number of places, larger than said first number of places, in a manner controlled by the divisor frequency, the factor of proportionality of said divisor frequency to the speed of the corresponding rotating member being chosen with respect to the corresponding proportionality factor of said dividend frequency and to the difference between said second and said first number of places, so that for the lowest quotient frequency in the expected range at least a predetermined minimum number of quotient pulses will be provided in each cycle of said first binary counter; storing the content of said second binary counter at intervals chosen so the content of said counter will have the desired proportional relation to the speed of one of said members, and resetting said secondary binary counter when said storage has been effected; adding the said stored content first to zero and then to the sum of the previous addition at intervals determined as set forth hereinbelow and registering the result of the addition in a register having said second number of places; comparing the content of said first binary counter with the n most significant binary digits in said register, n being equal to said first number of places, and producing a quotient frequency pulse whenever a match is thus found, and using the quotient frequency pulses to cause the last stored content of said second binary counter to be added to the content of said register and to advance said register to contain the new sum.
Claim 15
Independent Claim
318 words
A method of measuring the ratio or product of the speeds of two rotating members with one speed specified as dividend and the other as divisor, comprising the steps of: generating pulse trains of frequencies respectively proportioned to the speeds of said rotating members; driving a first binary counter of a first predetermined number of places with the dividend frequency; driving a second binary counter of a second predetermined number of places, larger than said first number of places, in a manner controlled by the divisor frequency, the factor of proportionality of said divisor frequency to the speed of the corresponding rotating member being chosen with respect to the corresponding proportionality factor of said dividend frequency and to the difference between said second and said first number of places, so that for the lowest quotient frequency in the expected range at least a predetermined minimum number of quotient pulses will be provided in each cycle of said first binary counter; storing the content of said second binary counter at intervals chosen so the content of said counter will have the desired proportional relation to the speed of one of said members, and resetting said secondary binary counter when said storage has been effected; adding the said stored content first to zero and then to the sum of the previous addition at intervals determined as set forth hereinbelow and registering the result of the addition in a register having said second number of places; comparing the content of said first binary counter with the n most significant binary digits in said register, n being equal to said first number of places, and producing a quotient frequency pulse whenever a match is thus found, and using the quotient frequency pulses to cause the last stored content of said second binary counter to be added to the content of said register and to advance said register to contain the new sum.
Claim 16
Dependent Claim
34 words
A method as defined in claim 13 in which said second number of places exceeds said first number of places by at least 4, whereby the maximum rounding error does not exceed 3 percent.
Claim 17
Dependent Claim
50 words
A method as defined in claim 13 in which said second binary counter is driven at a predetermined constant pulse rate and its content is stored and the counter reset at intervals corresponding to the period of a pulse train proportional to the period of rotation of said rotating members.
Claim 18
Dependent Claim
56 words
A method as defined in claim 13 in which said second binary counter is driven at a pulse rate proportional to the speed of rotation of one of said rotating members and in which the content of said second binary counter is stored and said second binary counter is immediately thereafter reset at predetermined fixed intervals.
References Cited (Backward Citations)
US3716794A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-15 | 1978-01-14 | 1978-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-15 | 1982-01-14 | 1982-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-15 | 1986-01-14 | 1986-07-16 | $7700.00 | Window Closed / Lapsed |