Patent US4340922A successfully refreshed from Google Patents.
US4340922A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interface circuit in conformity with EIA standards and implemented with an operational amplifier-like circuit
Assignee: International Business Machines Corp
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Filing: 1980-11-21
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Granted: 1982-07-20
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Expires: 2000-11-21
Abstract
Abstract An interface circuit for exchanging digital signals between two pieces of data processing equipment is provided in integrated form in accordance with international standards, such as EIA Standards. This is achieved through modification of an operational amplifier to adapt its use to the conditions and requirements of interface circuits.
Inventors
- 👤 Francois X. Delaporte
- 👤 Gerard M. Lebesnerais
- 👤 Jean-Pierre Pantani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01825; H03K19/01831; H03K17/00; H03K17/08; H03K17/082; H03K17/0826; H03K5/00; H03K5/01; H03K5/02
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
193 words
An interface circuit utilizing the stages of an operational amplifier circuit with said stages including an input differential converter stage having two input terminals E- and E+ and an output terminal coupled to a frequency compensation stage, said operational amplifier further including a voltage amplifier stage coupled to said frequency compensation stage and to positive and negative voltage follower stages with latter stages coupled via current limiting means to output terminal means, the improvement comprising; reference voltage means coupled to one of said two input terminals E- and E+; protection circuit means including first unilateral conducting means series connected with the positive terminal of said supply voltage and arranged to protect said operational amplifier circuit stages from positive and negative overvoltages in excess of the supply voltage occurring at said output terminal means and second unilateral conducting means coupled between said output terminal means and said first unilateral conducting means so as to protect said positive voltage follower stage and said current limiting means from positive overvoltages; and constant current bias circuit means coupled to bias said operational amplifier circuit stages at a constant bias voltage independent of overvoltages in said supply voltage.
Claim 2
Dependent Claim
193 words
An interface circuit utilizing the stages of an operational amplifier circuit with said stages including an input differential converter stage having two input terminals E- and E+ and an output terminal coupled to a frequency compensation stage, said operational amplifier further including a voltage amplifier stage coupled to said frequency compensation stage and to positive and negative voltage follower stages with latter stages coupled via current limiting means to output terminal means, the improvement comprising; reference voltage means coupled to one of said two input terminals E- and E+; protection circuit means including first unilateral conducting means series connected with the positive terminal of said supply voltage and arranged to protect said operational amplifier circuit stages from positive and negative overvoltages in excess of the supply voltage occurring at said output terminal means and second unilateral conducting means coupled between said output terminal means and said first unilateral conducting means so as to protect said positive voltage follower stage and said current limiting means from positive overvoltages; and constant current bias circuit means coupled to bias said operational amplifier circuit stages at a constant bias voltage independent of overvoltages in said supply voltage.
Claim 3
Dependent Claim
19 words
The interface circuit as set forth in claim 1 wherein said first unilateral conducting means comprises first diode means.
Claim 4
Dependent Claim
48 words
The interface circuit as set forth in claim 2 wherein said first diode means comprises a lateral PNP transistor the emitter of which is the anode of said first diode means and the base and collector coupled together of which is the cathode of said first diode means.
Claim 5
Dependent Claim
29 words
The interface circuit as set forth in claim 3 wherein said reference voltage means is coupled to the E+ input terminal of said two input terminals E- and E+.
Claim 6
Dependent Claim
28 words
The interface circuit as set forth in claim 1 wherein said protection circuit means further includes anti-breakdown current mirror circuit means for protecting said negative voltage follower stage.
Claim 7
Dependent Claim
98 words
The interface circuit as set forth in claim 5 wherein said negative voltage follower stage includes output transistor means and said anti-breakdown current mirror circuit means includes simulating transistor means arranged so that its emitter to collector voltage is substantially the same as the emitter to collector voltage of said output transistor means such that said simulating transistor means acts to simulate the leakage current of said output transistor means and allow said leakage current to be sunk via sinking means to the negative terminal of said supply voltage thereby avoiding its amplification by said output transistor means.
Claim 8
Dependent Claim
16 words
The interface circuit as set forth in claim 6 wherein said sinking means comprises transistor means.
Claim 9
Dependent Claim
30 words
The interface circuit as set forth in claim 6 wherein said protection circuit means further includes third unilateral conducting means series connected with the negative terminal of said supply voltage.
Claim 10
Dependent Claim
19 words
The interface circuit as set forth in claim 8 wherein said third unilateral conducting means comprises second diode means.
Claim 11
Dependent Claim
47 words
The interface circuit as set forth in claim 9 wherein said second diode means comprises NPN transistor means the collector of which is the cathode of said second diode means and the base and emitter coupled together of which is the anode of said second diode means.
Claim 12
Dependent Claim
35 words
The interface circuit as set forth in claim 10 further including drive circuit means for selectively stopping the transmission of data through said interface circuit by placing said interface circuit into a high impedance condition.
Claim 13
Dependent Claim
52 words
The interface circuit as set forth in claim 9 or 10 integrated in chip form in planar technology and characterized in that said second diode means is mounted around the periphery of said chip and is protected by a screen of epitaxial pockets in such a way as to trap injected carriers.
References Cited (Backward Citations)
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Cited
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Cited
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Cited
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Cited
US4178619A
Cited
FR2363215B3
Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-19 | 1986-01-18 | 1986-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-19 | 1990-01-18 | 1990-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-19 | 1994-01-18 | 1994-07-20 | $7700.00 | Window Closed / Lapsed |