Input overload protection circuit

Claim 2

An input overload protection circuit comprising: a high impedance differential amplifier having a pair of inputs; a pair of input conductors operatively connected to said respective pair of inputs of said differential amplifier for conducting signal thereto; a third conductor connected to a reference potential; a first serial plurality of diode-action clamping means connected intermediate one conductor of said pair and said third conductor; a second serial plurality of diode-action clamping means connected intermediate the other conductor of said pair and said third conductor; and guard means responsive to the respective signal voltage at that end of said respective first and second plurality of clamping means connected respectively to said one and said other conductors of said pair for applying substantially said respective signal voltage to said respective first and second plurality of clamping means intermediate the respective ends thereof, thereby to substantially prevent leakage current from flowing through said clamping means from said pair of conductors.

Claim 3

The protection circuit of claim 1 wherein at least one diode-action clamping means in both said first and second pluralities is common to both said first and second pluralities.

Claim 4

The protection circuit of claim 2 wherein said at least one clamping means common to both said first and second pluralities of clamping means includes that one connected most directly to said third conductor.

Claim 5

The protection circuit of claim 2 wherein said differential amplifier comprises a pair of operational amplifiers each having a different one of said pair of input conductors respectively connected to the noninverting input thereof, said input conductors applying substantially said respective signal voltages to said respective operational amplifier inputs, a first voltage divider network having its opposite ends connected to the respective outputs of said pair of operational amplifiers, and first and second spaced taps on said divider respectively connected to the inverting inputs of said pair of operational amplifiers for completing respective feedback paths thereto, the voltages appearing at said first and second taps being substantially the same as said signal voltages appearing on the respective conductors of said pair; and said guard means comprises a second voltage divider network having its opposite ends connected to the respective outputs of said pair of operational amplifiers and having respective first and second taps thereon with the same division ratio as said taps on said first voltage divider, said first and second taps of said second voltage divider being connected to apply said respective signal voltages to said respective first and second plurality of clamping means for preventing leakage current from flowing.

Claim 6

The protection circuit of claim 4 wherein both said first and second voltage divider networks are resistive, each having first, second and third resistances respectively divided by said first and second taps, said first and third resistances of each particular divider being of equal value.

Claim 7

The protection circuit of claim 3 including circuit element means intolerant of large currents and connected in series in at least one conductor of said pair intermediate said clamping means and the respective input to said amplifier, said current-intolerant means being adversely affected by currents above a small value, and series resistance means of low ohmic value in the respective said conductors between said clamping means and said current-intolerant element for limiting residual input current to the latter.