US4338676A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Asynchronous adder circuit
Assignee: AT&T Inc
•
Filing: 1980-07-14
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Granted: 1982-07-06
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Expires: 2000-07-14
Abstract
Abstract An adder circuit for generating a completion signal indicating the completion of adder operation. A detector circuit (103) is connected to the power supply bus (102) of a multistage parallel adder for detecting voltage variations caused by the operation of the adder stages and for generating a completion signal when these voltage variations have ceased to occur for a predetermined period of time.
Inventors
- 👤 Bruce E. Briley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:04
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5052
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
71 words
An electrical circuit comprising: a power supply bus (102); and logic circuit means (101 n ) connected to said bus and causing voltage variations on said bus during the performance of logic operations; characterized in that said electrical circuit further comprises detector means (103) coupled to said bus for detecting said variations and for generating a completion signal indicating completion of said logic operations, after said variations have ceased to occur.
Claim 2
Dependent Claim
71 words
An electrical circuit comprising: a power supply bus (102); and logic circuit means (101 n ) connected to said bus and causing voltage variations on said bus during the performance of logic operations; characterized in that said electrical circuit further comprises detector means (103) coupled to said bus for detecting said variations and for generating a completion signal indicating completion of said logic operations, after said variations have ceased to occur.
Claim 3
Dependent Claim
37 words
An electrical circuit as claimed in claim 1 further characterized in that said logic circuit means comprises a plurality of logic gates (131, . . . 139) interconnected to form an arithmetic circuit for performing arithmetic functions.
Claim 4
Dependent Claim
57 words
An electrical circuit as claimed in claim 1 further characterized in that said logic circuit means comprises a plurality of logic gates (131, . . . 139) each including a pair of cascaded transistors (335, 336) connected between said bus and ground whereby said voltage variations are caused on said bus during operation of said cascaded transistors.
Claim 5
Dependent Claim
22 words
An electrical circuit as claimed in claim 3 further characterized in that said logic gates are interconnected to form an arithmetic circuit.
Claim 6
Dependent Claim
68 words
An electrical circuit as claimed in claim 1 further characterized in that said logic circuit means comprises a plurality of interconnected adder stages (101 1 , . . . 101 n ) connected to said bus and said detector means comprises timing means (106, 107, 108, 114, 115) for generating said completion signal a predetermined period after the last of a plurality of said variations has been detected.
Claim 7
Dependent Claim
31 words
An electrical circuit as claimed in claim 1 further characterized in that said detector means comprises a detector circuit responsive to said variations when said variations exceed a first predetermined level.
Claim 8
Dependent Claim
77 words
An electrical circuit as claimed in claim 6 further characterized in that said detector circuit comprises: a first switching comparator circuit (104, 105) responsive to said variations for generating a comparator output signal for each of said voltage variations which exceed said first predetermined level, and a timing circuit (106, 107, 108) connected to said first switching comparator circuit for generating said completion signal in the absence of comparator output signals for a predetermined period of time.
Claim 9
Dependent Claim
82 words
An electrical circuit as claimed in claim 7 further characterized in that said timing circuit comprises: timer means (106, 114, 115) connected to said first switching comparator circuit for generating a timer output signal which exceeds a second predetermined level only when comparator output signals have been absent for said predetermined period of time, and a second switching comparator circuit (107, 108) connected to said timer means for generating said completion signal when said timer output signal exceeds said second predetermined level.
Claim 10
Dependent Claim
52 words
An electrical circuit as claimed in claim 8 further characterized in that said first and second switching comparator circuits each comprise a pair of emitter-coupled transistors (104-105, 107-108) whereby the emitter of one of the transistors of a pair is coupled to the emitter of the other transistor of the same pair.
Claim 11
Dependent Claim
82 words
An electrical circuit as claimed in claim 8 further characterized in that said timer means is reset upon the occurrence of each of said comparator output signals and comprises: a transistor (106) having its base connected to said first switching comparator circuit and a capacitor (115) connected to said transistor, and said second switching comparator for generating said timer output signal, said transistor being responsive to said comparator output signals to discharge said capacitor each time a comparator output signal is generated.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-05 | 1986-01-04 | 1986-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-05 | 1990-01-04 | 1990-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-05 | 1994-01-04 | 1994-07-06 | $7700.00 | Window Closed / Lapsed |