Binary parallel computing arrangement for additions or subtractions

Claim 2

A parallel binary computing arrangement comprising: an adder having a plurality of stages with sequential carry propagation between stages, each stage receiving corresponding digit positions of two operands, a plurality of detection circuits distributed over the stages of said adder, each said detection circuit receiving the operand digits of at least one digit position of each operand for providing a detector output signal indicating the beginning or the end of a carry ripple by testing the condition "both operand digits 0 or both operand digits 1", a coder connected and responsive to the output signals of said detection circuits for providing one of a plurality of group indicating signals, each of which corresponds to a predetermined distance of possible carry ripples between digit positions, a clock including pulse generating means for providing a repeatable sequence of a predetermined number of time pulses; and clock modifying means, responsive to said group indicating signals from said coder for selectively skipping certain of said time pulses, whereby the operating time between the starting time of said clock sequence if limited to the duration of the carry ripple over the shortest digit position distance determined by said detection circuits.

Claim 3

A computing arrangement in accordance with claim 1, wherein: each of said detection circuits is associated with, and connected to, a group of adjacent digit positions, said detection circuits being distributed in such a manner that a uniform number of digit positions are unconnected on both sides of each such group.

Claim 4

A computing arrangement in accordance with claim 2 wherein: each said detection circuit is connected to four adjacent digit positions.

Claim 5

a computing arrangement in accordance with claim 3 wherein: each of said detection circuits include an EXCLUSIVE OR circuit for each digit position, said EXCLUSIVE OR circuit receiving a digit from one operand in a true form and a digit from the other operand in a negated form.

Claim 6

A computing arrangement in accordance with claim 4 wherein each of said detection circuits further includes: an OR circuit connected, and responsive to, said EXCLUSIVE OR circuits for providing said detector output signal.

Claim 7

Computing arrangement in accordance with claim 5 wherein said coder includes: first, second, third, and fourth group indicating means connected to said detection circuit means, said first group indicating means responding to an output from all said detection circuits for providing a first group indicating signal which serves to select a first operating time, said second group indicating means responding to the absence of an output from one of said detection circuits and an output of two adjacent ones of said detection circuits, or from the positive output signal of said one detection circuit and the absence of an output from at least one of said adjacent detection circuits for producing a second group indicating signal which serves to select a second operating time that is longer than the first operating time, said third group indicating means responding to the absence of an output from two adjacent ones of said detection circuits for producing a third group indicating signal which serves to select a third operating time exceeding the second operating time, and said fourth group indicating means responding to the absence of an output from all said detection circuits for producing a fourth indicating signal which serves to select a fourth operating time exceeding all the other operating times.

Claim 8

A computing arrangement in accordance with claim 6 wherein said clock includes: a counter; and said clock modifying means further includes means connected between said coder and said counter for generating increment signals of different values in accordance with the one of said group indicating signals generated, whereby said counter is caused to skip individual clock cycles.

Claim 9

A computing arrangement in accordance with claim 7 wherein said counter includes: a register circuit for storing the current clock count; and an adder connected to said register and said clock modifying means, which forms a loop together with the register circuit, and which receives the current clock count together with said increment signals as input operands.