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US4336468A
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Simplified combinational logic circuits and method of designing same
Assignee: University of California, San Diego
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Filing: 1979-11-15
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Granted: 1982-06-22
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Expires: 1999-11-15
Abstract
Abstract A logic circuit and method for implementing a given, partially symmetric Boolean function f(x1-xn) which is pairwise symmetric with respect to at least one pair xixj of variables such that the function is invariant under their permutation. The circuit includes a symmetric logic array having a transposition gate for each pair xixj, and a combinational logic circuit connected to the output of each transposition gate. The latter filters redundant values of each pair xixj and these values are used in the design of the combinational logic circuit. The invention simplifies or minimizes the gating for performing the function.
Inventors
- 👤 Richard Spillman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:54
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
96 words
A logic circuit for implementing a given, partially symmetric Boolean function f(x 1 -x n ) having one output and which is symmetric with respect to several variables of the input variables x 1 -x n such that the function is invariant under the permutation of the several variables, comprising: (a) symmetric logic means for filtering only redundant values of the several variables, the redundant values being "don't cares"; and (b) combinational logic means, connected to said symmetric logic means, for generating the one output and having a construction as a function of the "don't cares".
Claim 2
Dependent Claim
96 words
A logic circuit for implementing a given, partially symmetric Boolean function f(x 1 -x n ) having one output and which is symmetric with respect to several variables of the input variables x 1 -x n such that the function is invariant under the permutation of the several variables, comprising: (a) symmetric logic means for filtering only redundant values of the several variables, the redundant values being "don't cares"; and (b) combinational logic means, connected to said symmetric logic means, for generating the one output and having a construction as a function of the "don't cares".
Claim 3
Dependent Claim
33 words
A logic circuit according to claim 1 wherein said symmetric logic means comprises transposition logic gate means, having two inputs and two outputs, for gating a pair of variables of the several variables.
Claim 4
Dependent Claim
38 words
A logic circuit according to claim 2 wherein the pair of variables has two minterms and wherein said transposition logic gate means comprises an AND gate and an OR gate being connected to filter one of the minterms.
Claim 5
Dependent Claim
130 words
A logic circuit for implementing a given, partially symmetric, Boolean function f(x 1 -x n ) having one output and which is pairwise symmetric with respect to at least one pair x i x j of input variables x 1 -x n such that the function f(x 1 -x n ) is invariant under the permutation of x i x j , comprising: (a) symmetric logic array means, responsive to each said pair x i x j of input variables x 1 -x n , for filtering redundant values of said pair x i x j , the redundant values being "don't cares"; and (b) combinational logic gate means, connected to said symmetric logic array means, for generating the output and being constructed as a function of the "don't cares".
Claim 6
Dependent Claim
130 words
A logic circuit for implementing a given, partially symmetric, Boolean function f(x 1 -x n ) having one output and which is pairwise symmetric with respect to at least one pair x i x j of input variables x 1 -x n such that the function f(x 1 -x n ) is invariant under the permutation of x i x j , comprising: (a) symmetric logic array means, responsive to each said pair x i x j of input variables x 1 -x n , for filtering redundant values of said pair x i x j , the redundant values being "don't cares"; and (b) combinational logic gate means, connected to said symmetric logic array means, for generating the output and being constructed as a function of the "don't cares".
Claim 7
Dependent Claim
27 words
A logic circuit according to claim 4 wherein said symmetric logic array means comprises a transposition logic gate for each said pair x i x j .
Claim 8
Dependent Claim
45 words
A logic circuit according to claim 5 wherein each said pair x i x j has two minterms 1 0 and 0 1, and each said transposition logic gate includes an AND gate and an OR gate being connected to filter one of the minterms.
Claim 9
Independent Claim
127 words
A method of implementing a given partially symmetric Boolean function f(x 1 -x n ) having a set S of at least one element, in which each element has several of the variables x 1 -x n such that the function f(x 1 -x n ) is invariant under the permutation of the several variables in each element, comprising: (a) determining the set S; (b) designing a symmetric logic means for filtering redundant values of the variables of each element, the redundant values being "don't cares", (c) designing a combinational logic means as a function of the "don't cares"; and (d) constructing a logic circuit having the symmetric logic means and the combinational logic means being connected together to implement the function f(x 1 -x n ).
Claim 10
Independent Claim
127 words
A method of implementing a given partially symmetric Boolean function f(x 1 -x n ) having a set S of at least one element, in which each element has several of the variables x 1 -x n such that the function f(x 1 -x n ) is invariant under the permutation of the several variables in each element, comprising: (a) determining the set S; (b) designing a symmetric logic means for filtering redundant values of the variables of each element, the redundant values being "don't cares", (c) designing a combinational logic means as a function of the "don't cares"; and (d) constructing a logic circuit having the symmetric logic means and the combinational logic means being connected together to implement the function f(x 1 -x n ).
Claim 11
Dependent Claim
26 words
A method according to claim 7 wherein the step of designing the combinational logic means comprises using the "don't cares" to simplify the combinational logic means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-21 | 1985-12-21 | 1986-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-21 | 1989-12-21 | 1990-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-21 | 1993-12-21 | 1994-06-22 | $7700.00 | Window Closed / Lapsed |