US4336461A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fail-safe apparatus
Assignee: EIDP Inc
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Filing: 1980-09-22
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Granted: 1982-06-22
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Expires: 2000-09-22
Abstract
Abstract A fail-safe logic circuit which includes a pulse generator driven series arrangement of opto-isolators each of which generates a pulsating signal at its output as a function of the logic level state of its respective input terminal. If all input terminals are logic level highs, then a pulsating output signal is equivalent to a true state whereas either a DC or zero level signal is indicative of a false state.
Inventors
- 👤 Edward S. Ida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:57
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/007
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
130 words
A fail-safe circuit comprising: (a) a first opto-isolator having a gain of at least unity and having input switching element, output switching element and input LED element terminals; (b) a second opto-isolator having a gain of at least unity and having input switching element, output switching element and input LED element terminals, said input LED element terminal of said second opto-isolator being connected to the output switching element terminal of said first opto-isolator; (c) a pulsating signal source connected to the input LED element terminal of said first opto-isolator; (d) means for simultaneously applying a DC high binary logic level signal to the input switching element terminals of said first and second opto-isolator whereby a pulsating logic signal is generated at the output switching element terminal of said second opto-isolator.
Claim 2
Dependent Claim
130 words
A fail-safe circuit comprising: (a) a first opto-isolator having a gain of at least unity and having input switching element, output switching element and input LED element terminals; (b) a second opto-isolator having a gain of at least unity and having input switching element, output switching element and input LED element terminals, said input LED element terminal of said second opto-isolator being connected to the output switching element terminal of said first opto-isolator; (c) a pulsating signal source connected to the input LED element terminal of said first opto-isolator; (d) means for simultaneously applying a DC high binary logic level signal to the input switching element terminals of said first and second opto-isolator whereby a pulsating logic signal is generated at the output switching element terminal of said second opto-isolator.
Claim 3
Dependent Claim
29 words
The circuit of claim 1, wherein the pulsating logic signal at the output switching element terminal of the second opto-isolator is input to a fail-safe pulse to DC converter.
Claim 4
Dependent Claim
184 words
The circuit of claim 2, wherein said fail-safe pulse to DC converter, comprises: (a) a third opto-isolator haing its LED element connected between a DC voltage supply and the output terminal of said second opto-isolator, its one switching element terminal connected to circuit common, and its other switching element terminal generating an amplified pulsating signal in phase with said output pulsating logic signal from said second opto-isolator; an input capacitor with one terminal joining said other switching element terminal of said third opto-isolator; a constant current generator connected to the junction of said input capacitor and said third opto-isolator for maintaining a positive polarity signal at the other terminal of said input capacitor using a negative DC voltage supply; (b) first and second diodes in series connection with the anode of the first joining the cathode of the second and said diode junction connected to the other terminal of said input capacitor; and (c) an output charge storage means spanning said series connected diodes such that one terminal of said charge storage means joins the anode of the second said diode to circuit common.
Claim 5
Dependent Claim
20 words
The circuit of claim 3, wherein said charge storage means is an RC parallel network having a selectable time constant.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-21 | 1985-12-21 | 1986-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-21 | 1989-12-21 | 1990-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-21 | 1993-12-21 | 1994-06-22 | $7700.00 | Window Closed / Lapsed |