US4097764A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fail-safe solid state logic
Assignee: SASIB SpA Bologna
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Filing: 1977-03-18
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Granted: 1978-06-27
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Expires: 1997-03-18
Abstract
Abstract A fail-safe solid state logic system based on the use of an AC input signal of one type, and a DC input which causes a logical gate to convert the AC input signal to a totally different AC output signal; that is, to one adapted to be received by a vital driver or the like, which is tuned to accept only that different AC output signal and no other. Accordingly, the failures which are most likely to occur, namely, shorts from input to output or failure to toggle, result in the AC signal frequency not being changed and as a consequence, the system fails safe.
Inventors
- 👤 Henry C. Sibley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:38
CPC Classifications
H; H02; H02H; H02H3/00; H02H3/02; H02H3/05; B; B61; B61L; B61L1/00; B61L1/20; H03; H03K; H03K19/00; H03K19/007
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
169 words
A fail-safe logic device, comprising a solid state, toggle flip-flop AND gate having an output at which a binary one signal appears provided a first AC digital signal, representative of a binary one, applied to a first input occurs concurrently with another digital signal, also representative of a binary one, applied to a second input; first means for applying such first AC digital signal to said first logic input of said device; second means for applying said other digital signal at a DC voltage power supply terminal of said logic device as a second logic input of said device; a vital driver coupled to said output of said toggle flip-flop AND gate, said vital driver being operative to accept only an output AC signal which is one-half the frequency of the AC digital signal at the first input, whereby any lack of conversion, due to a short or the like from input to output, will result in rejection of the unconverted, or wrong-frequency, signal then appearing at said output.
Claim 2
Dependent Claim
169 words
A fail-safe logic device, comprising a solid state, toggle flip-flop AND gate having an output at which a binary one signal appears provided a first AC digital signal, representative of a binary one, applied to a first input occurs concurrently with another digital signal, also representative of a binary one, applied to a second input; first means for applying such first AC digital signal to said first logic input of said device; second means for applying said other digital signal at a DC voltage power supply terminal of said logic device as a second logic input of said device; a vital driver coupled to said output of said toggle flip-flop AND gate, said vital driver being operative to accept only an output AC signal which is one-half the frequency of the AC digital signal at the first input, whereby any lack of conversion, due to a short or the like from input to output, will result in rejection of the unconverted, or wrong-frequency, signal then appearing at said output.
Claim 3
Dependent Claim
39 words
A device as defined in claim 1, further including means connected between said toggle flip-flop AND gate and said second digital signal-applying means for rendering operative said AND gate, whereby any lack of conversion disconnects said DC voltage supply.
Claim 4
Dependent Claim
131 words
A fail-safe logic device, comprising a plurality of toggle flip-flop AND gates as defined in claim 1; a vital driver coupled to the output of a first of said toggle flip-flop AND gates; means for feeding back a DC signal from said vital driver to said first of said AND gates in response to a signal originating at the input of a second of said AND gates; an OR circuit connected to both of said AND gates so as to transmit either the output from said first or from said second AND gate to said vital driver; a toggle flip-flop forming part of said OR circuit and connected to said vital driver for halving the input frequency thereto so as to obtain the signal of predetermined frequency for said vital driver.
Claim 5
Dependent Claim
36 words
An apparatus as defined in claim 3, further including a pair of channels or paths, each comprising a pair of lines, connected to said OR circuit and a frequency doubling device in each of said paths.
Claim 6
Dependent Claim
36 words
Apparatus as defined in claim 4, further including a third toggle flip-flop AND gate having a clock source connected to its input, its output being connected to the input of said first toggle flip-flop AND gate.
Claim 7
Dependent Claim
52 words
Apparatus as defined in claim 3, in which said vital driver is energized so long as a set input signal exists at said first AND gate OR a hold input signal exists at said second AND gate and the precondition of the concurrent appearance of a set input signal has been fulfilled.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-26 | 1981-12-26 | 1982-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-26 | 1985-12-26 | 1986-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-26 | 1989-12-26 | 1990-06-27 | $7700.00 | Window Closed / Lapsed |