Binary divider circuit for electronic watch

Claim 1

An electronic watch comprising time standard oscillator means for producing a high frequency signal; a binary divider chain means connected to said oscillator means for receiving said high frequency signal and for dividing said high frequency signal into low frequency timing signals, said divider chain means including at least one binary divider formed from dual OR-NAND gates and first and second inverter means formed from COS/MOS integrated circuits, each said OR-NAND gate including a source of voltage; a ground; a pair of first P channel MOS transistors (1a, 1b) having their respective source electrodes connected in common to said source of voltage; a pair of second P channel MOS transistors (2a, 2b) having their respective source electrodes connected respectively to the drain electrodes of said pair of first P channel MOS transistors (1a, 1b); a pair of first N channel MOS transistors (3a, 3b) having their respective drain electrodes connected together and connected to a common connection of the respective drain electrodes of said pair of second P channel MOS transistors (2a, 2b); and a pair of second N channel MOS transistors (4a, 4b) having their respective drain electrodes connected together and to the common connection of the source electrodes of said pair of first N channel MOS transistors (3a, 3b), the respective source electrodes of said pair of second N channel MOS transistors being connected together to said ground, the gate electrodes of one of said second P channel MOS transistors (2a) and one of said first N channel MOS transistors (3b) being connected together to define a first input, the gate electrodes of one of said first P channel MOS transistors (1a) and the other of said first N channel MOS transistors (3a) being connected together to define a second input, the gate electrodes of the other of said first P channel MOS transistors (1b) and one of said second N channel MOS transistors (4b) being connected together to define a third input, the gate electrodes of the other of said second P channel MOS transistors (2b) and the other of said second N channel MOS transistors (4a) being connected together to define a fourth input, the common connection between the respective drain electrodes of the pair of first N channel MOS transistors (3a, 3b) and the pair of second P channel MOS transistors (2a, 2b) defining an output terminal, said dual ORNAND gates including two of said OR-NAND gates, a single pair of said first P channel MOS transistors (1a, 1b) and a single pair of said second N channel MOS transistors (4a, 4b) being incorporated in both of said OR-NAND gates, a first divider input being defined by the common connection of the fourth inputs of both of said OR-NAND gates, a second divider input being defined by the common connection of both of said second inputs of said OR-NAND gates, the output terminal of one of said OR-NAND gates beIng connected through said first inverter means to the common connection defining the third inputs of both of said OR-NAND gates, the output terminal of the other of said OR-NAND gates defining a divider output terminal and being connected directly to the first input of said one of said OR-NAND gates and being connected through said second inverter means to the first input of said other of said OR-NAND gates.