US3619644A
Expired / Lapsed
US
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Frequency dividing circuit
Assignee: Centre Electronique Horloger SA
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Filing: 1970-10-14
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Granted: 1971-11-09
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Expires: 1990-10-14
Abstract
Abstract A frequency dividing circuit comprises at least one logic structure satisfying the Boolian relationships A BI1+AI2 and B BI1+AI2 in which I1 and I2 are two complementary input quantities and A and B two output quantities. The logic structure comprises three pairs of field effect transistors each having a source, a drain and a gate, and two outputs each connected to the drains of the two transistors of the first pair and the second pair respectively. The sources of one transistor of the first pair and of one transistor of the second pair are separately connected to the drain of one of the transistors of the third pair, the sources of the two other transistors of the first and second pairs are connected together to the drain of a seventh transistor, and the sources of the two transistors of the third pair and of the seventh transistor are connected to a terminal of a voltage source.
Inventors
- 👤 Eric Andre Vittoz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:17
CPC Classifications
H; H03; H03B; H03B19/00; H03B19/06; H03B19/14; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
159 words
A frequency dividing circuit comprising at least one logic structure satisfying the Boolian relationships A BI1+AI2 and B BI1+AI2 in which I1 and I2 are two complementary input quantities and A and B two output quantities, the logic structure comprising three pairs of field effect transistors (17-18; 19-20; 22-23) each having a source, a drain and a gate, and two outputs (A,B) each connected to the drains of the two transistors of the first pair and the second pair respectively, the sources of a transistor (18) of the first pair and of a transistor (19) of the second pair being separately connected to the drain of one of the transistors (22,23) of the third pair, and the sources of the two other transistors (17,20) being connected together to the drain of a seventh transistor (29), the sources of the two transistors of the third pair and of the seventh transistor being connected to a terminal of a voltage source.
Claim 2
Dependent Claim
159 words
A frequency dividing circuit comprising at least one logic structure satisfying the Boolian relationships A BI1+AI2 and B BI1+AI2 in which I1 and I2 are two complementary input quantities and A and B two output quantities, the logic structure comprising three pairs of field effect transistors (17-18; 19-20; 22-23) each having a source, a drain and a gate, and two outputs (A,B) each connected to the drains of the two transistors of the first pair and the second pair respectively, the sources of a transistor (18) of the first pair and of a transistor (19) of the second pair being separately connected to the drain of one of the transistors (22,23) of the third pair, and the sources of the two other transistors (17,20) being connected together to the drain of a seventh transistor (29), the sources of the two transistors of the third pair and of the seventh transistor being connected to a terminal of a voltage source.
Claim 3
Dependent Claim
132 words
A circuit according to claim 1, comprising fourth, fifth, sixth and seventh pairs of field effect transistors (9-10; 11-12; 13-14; 15-16), the two sources and the two drains of each pair being respectively connected together, the sources of the fourth pair (9-10) and fifth pair (11-12) being connected to the other terminal of the said voltage source, the drains of the fourth and fifth pairs being respectively connected to the sources of the sixth pair (13-14) and the seventh pair (15-16) the drains of which are connected to the drains of the first pair (17-18) and the second pair (19-20), the transistors of the three first pairs as well as the said seventh transistor being of a type opposed to that of the transistors of the fourth, fifth, sixth and seventh pairs.
Claim 4
Dependent Claim
23 words
A circuit according to claim 2, comprising two inversers (25-26; 27-28) each formed by a pair of field effect transistor of opposed types.
Claim 5
Dependent Claim
77 words
A circuit according to claim 2, comprising two inversers (25-26; 27-28) each formed by a pair of field effect transistors, of opposed types, and a plurality of binary stages, the circuit being provided in integrated form in one and the same substrate, the n-type transistors of all of the stages being formed in a p-type region of the substrate and the p-type transistors of all of the stages being formed in an n-type region of this substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-08 | 1975-05-10 | 1975-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-08 | 1979-05-10 | 1979-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-08 | 1983-05-10 | 1983-11-09 | $7700.00 | Window Closed / Lapsed |