US4335374A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Key discrimination circuit
Assignee: Panasonic Holdings Corp
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Filing: 1980-06-09
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Granted: 1982-06-15
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Expires: 2000-06-09
Abstract
Abstract A key discrimination circuit for determining which key among a plurality of keys disposed in a matrix is actuated and which generates less electrical noise than prior art key discrimination circuits. In prior art key discrimination circuits, one set of lines forming the key matrix are continuously scanned while a plurality of AND gates are cyclically enabled thereby determining the actuated key or keys according to the time an output signal is generated. Because the continuously scanned set of lines are long and have "1" and "0" level signals periodically appearing thereon, they tend to generate electrical noise. In the key discrimination circuit of the present invention, initially all the lines in one set of lines have a "1" level applied thereto. A separate circuit determines when any key is actuated. Only when it is determined that at least one key is actuated is the key matrix scanned to determine the key or keys actuated. Therefore, the set of lines are intermittently scanned only when it is necessary to determine which key is actuated, thereby reducing the electrical noise generation.
Inventors
- 👤 Tomoaki Nyuji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:59
CPC Classifications
H; H03; H03M; H03M11/00; H03M11/20
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
538 words
A key discrimination circuit comprising: a plurality of key input signal lines; a plurality of key output signal lines mutually crossed with said plurality of key input signal lines in a matrix; a plurality of key switches each coupled to a corresponding one of said key input signal lines and to a corresponding one of said key output signal lines for manually switching an electrical connection between said corresponding key input signal lines and said corresponding key output signal lines; a plurality of first OR gates, each having an output terminal connected to a corresponding one of said key input signal lines, a first input terminal and a second input terminal; a R-S flip-flop having an output terminal connected to said first input terminal of each of said first OR gates, a set terminal and a reset terminal; a second OR gate, having a plurality of input terminals each connected to a corresponding one of said key output signal lines and an output terminal, for producing an output signal "1" at said output terminal when one of said key switches is manually operated to connect said corresponding key input signal line and said corresponding key output signal line, and for producing an output signal "0" at said output terminal when none of said key switches is manually operated; a plurality of AND gates, each having a first input terminal connected to a corresponding one of said key output signal lines, a second input terminal and an output terminal; a third OR gate having a plurality of input terminals, each connected to said output terminal of a corresponding one of said AND gates, and an output terminal; a first stage discrimination detector connected to said output terminal of said second OR gate and said reset terminal of said R-S flip-flop and having a trigger output terminal, for resetting said R-S flip-flop and for generating a trigger signal at said trigger output terminal when said second OR gate produces an output signal "1" at said output terminal thereof; and a scanning means connected to said second input terminals of said plurality of first OR gates, said set terminal of said R-S flip-flop, said second input terminals of said plurality of AND gates, said output terminal of said third OR gate, and said trigger output terminal of said first stage discrimination detector, and having an output terminal, for scanning said plurality of key switches by application of a "1" level pulse signal to successive ones of said second input terminals of said plurality of first OR gates for a predetermined period, during which period said scanning means further applies a "1" level signal to each of said second input terminals of said plurality of AND gates successively in turn, and thereafter applying a "1" level pulse signal to said set terminal of said R-S flip-flop when said first stage discrimination detector generates said trigger signal and for generating an output signal at said output terminal of said scanning means indicative of the key switches among said plurality of key switches manually switched from the time of generation of a "1" level signal at said output terminal of said third OR gate relative to said scan of said plurality of key switches.
Claim 2
Dependent Claim
538 words
A key discrimination circuit comprising: a plurality of key input signal lines; a plurality of key output signal lines mutually crossed with said plurality of key input signal lines in a matrix; a plurality of key switches each coupled to a corresponding one of said key input signal lines and to a corresponding one of said key output signal lines for manually switching an electrical connection between said corresponding key input signal lines and said corresponding key output signal lines; a plurality of first OR gates, each having an output terminal connected to a corresponding one of said key input signal lines, a first input terminal and a second input terminal; a R-S flip-flop having an output terminal connected to said first input terminal of each of said first OR gates, a set terminal and a reset terminal; a second OR gate, having a plurality of input terminals each connected to a corresponding one of said key output signal lines and an output terminal, for producing an output signal "1" at said output terminal when one of said key switches is manually operated to connect said corresponding key input signal line and said corresponding key output signal line, and for producing an output signal "0" at said output terminal when none of said key switches is manually operated; a plurality of AND gates, each having a first input terminal connected to a corresponding one of said key output signal lines, a second input terminal and an output terminal; a third OR gate having a plurality of input terminals, each connected to said output terminal of a corresponding one of said AND gates, and an output terminal; a first stage discrimination detector connected to said output terminal of said second OR gate and said reset terminal of said R-S flip-flop and having a trigger output terminal, for resetting said R-S flip-flop and for generating a trigger signal at said trigger output terminal when said second OR gate produces an output signal "1" at said output terminal thereof; and a scanning means connected to said second input terminals of said plurality of first OR gates, said set terminal of said R-S flip-flop, said second input terminals of said plurality of AND gates, said output terminal of said third OR gate, and said trigger output terminal of said first stage discrimination detector, and having an output terminal, for scanning said plurality of key switches by application of a "1" level pulse signal to successive ones of said second input terminals of said plurality of first OR gates for a predetermined period, during which period said scanning means further applies a "1" level signal to each of said second input terminals of said plurality of AND gates successively in turn, and thereafter applying a "1" level pulse signal to said set terminal of said R-S flip-flop when said first stage discrimination detector generates said trigger signal and for generating an output signal at said output terminal of said scanning means indicative of the key switches among said plurality of key switches manually switched from the time of generation of a "1" level signal at said output terminal of said third OR gate relative to said scan of said plurality of key switches.
Claim 3
Dependent Claim
147 words
A key discrimination circuit as claimed in claim 1, wherein: at least one of said connections between said scanning means and said second terminals of said plurality of first OR gates comprises a further R-S flip-flop having an output terminal connected to said second input terminal of one of said plurality of first OR gates, a set input terminal connected to said scanning means and a reset terminal; and said scanning means further comprises a further R-S flip-flop reset output terminal connected to said reset terminal of said further R-S flip-flop for resetting said further R-S flip-flop by application of a "1" level pulse signal to said reset terminal of said further R-S flip-flop upon determination that a key switch corresponding to said key input signal line connected to one of said plurality of first OR gates connected to said further R-S flip-flop is not manually switched.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-14 | 1985-12-14 | 1986-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-14 | 1989-12-14 | 1990-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-14 | 1993-12-14 | 1994-06-15 | $7700.00 | Window Closed / Lapsed |