US3900845A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Key input circuit
Assignee: Hitachi Ltd
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Filing: 1973-07-23
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Granted: 1975-08-19
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Expires: 1993-07-23
Abstract
Abstract A key input circuit includes a read control circuit, a memory circuit, and a key signal detector circuit. The memory circuit stores key signals read by the read control circuit. When the key signal detector circuit detects that any key signal has been stored in the memory circuit, it prevents key signals from being thereafter supplied from the read control circuit to the memory circuit. Thus, an erroneous input of the key signal due to simultaneous depression of two or more keys is avoided.
Inventors
- 👤 Takao Tsuiki
- 👤 Yoshikazu Hatsukano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:16
CPC Classifications
H; H03; H03M; H03M11/00; H03M11/20
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
140 words
A key input circuit comprising key controlled means for providing respective key signals representing selective key actuation, said key controlled means comprising a plurality of keys, timing pulse generator means for generating a series of sequential timing pulses and means for applying a respective timing pulse to one terminal of each of said keys, another terminal of each of said keys being connected together to a common terminal providing said key signals; read control circuit means responsive to said key signals for generating respective output signals, said read control circuit means comprising a plurality of AND gates each directly receiving the output of said common terminal, a respective one of said timing pulses and a control signal; and gate means responsive to said output signals for generating said control signal to inhibit further operation of said read control circuit means.
Claim 2
Dependent Claim
140 words
A key input circuit comprising key controlled means for providing respective key signals representing selective key actuation, said key controlled means comprising a plurality of keys, timing pulse generator means for generating a series of sequential timing pulses and means for applying a respective timing pulse to one terminal of each of said keys, another terminal of each of said keys being connected together to a common terminal providing said key signals; read control circuit means responsive to said key signals for generating respective output signals, said read control circuit means comprising a plurality of AND gates each directly receiving the output of said common terminal, a respective one of said timing pulses and a control signal; and gate means responsive to said output signals for generating said control signal to inhibit further operation of said read control circuit means.
Claim 3
Dependent Claim
32 words
A key input circuit as defined in claim 1, further comprising memory means for storing said output signals, said gate means being connected to receive the data stored in said memory means.
Claim 4
Dependent Claim
34 words
A key input circuit as defined in claim 2, further comprising encoder means connected between said read control circuit means and said memory means for converting said output signals to a predetermined binary code.
Claim 5
Dependent Claim
84 words
A key input circuit as defined in claim 3, wherein said encoder means comprises a plurality of logic gates receiving said output signals from said read control circuit means, and an AND gate receiving the output from one of said logic gates and a timing pulse from said timing pulse generator means having a pulse width not shorter than one of said sequential timing pulses, the outputs of the other of said logic gates and said AND gate being applied to said memory means.
Claim 6
Dependent Claim
32 words
A key input circuits as defined in claim 2, further comprising encoder means connected between said memory means and said gate means for converting said output signals to a predetermined binary code.
Claim 7
Dependent Claim
82 words
A key input circuit as defined in claim 2, wherein said read control circuit means comprises an additional plurality of keys each having a respective timing pulse applied to one terminal thereof and having another terminal thereof connected to an additional common terminal providing additional key signals, and further including key input means for connecting said common terminal and said additional common terminal to said read control circuit means during alternate time periods equal to a full sequence of said timing pulses.
Claim 8
Dependent Claim
50 words
A key input circuit as defined in claim 6, further comprising start pulse generator means responsive to the output of said key input means for generating a start pulse and means for applying said start pulse in common to all of the AND gates of said read control circuit means.
Claim 9
Dependent Claim
45 words
A key input circuit as defined in claim 1, wherein said key controlled means is a multiplexing circuit for time dividing said key signals on a common output and said read control circuit means is a de-multiplexer for providing said output signals on respective outputs.
Claim 10
Dependent Claim
111 words
A key input circuit comprising a plurality of keys, the output terminals of which are connected in common, read control circuit means comprising a plurality of AND gates each receiving the output of said commonly connected output terminals of the keys, memory circuit means receiving and storing a key signal indicative of the outputs of said read control circuit means, gate means having its input connected to said memory circuit means, its output connected to respective inputs of all of said AND gates and being responsive to any key signal sTored in the memory circuit for closing the AND gates when a key signal is stored in said memory circuit means.
Claim 11
Dependent Claim
111 words
A key input circuit comprising a plurality of keys, the output terminals of which are connected in common, read control circuit means comprising a plurality of AND gates each receiving the output of said commonly connected output terminals of the keys, memory circuit means receiving and storing a key signal indicative of the outputs of said read control circuit means, gate means having its input connected to said memory circuit means, its output connected to respective inputs of all of said AND gates and being responsive to any key signal sTored in the memory circuit for closing the AND gates when a key signal is stored in said memory circuit means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-18 | 1979-02-17 | 1979-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-18 | 1983-02-17 | 1983-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-18 | 1987-02-17 | 1987-08-19 | $7700.00 | Window Closed / Lapsed |