US4334348A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Retro-etch process for forming gate electrodes of MOS integrated circuits
Assignee: EMC Corp
•
Filing: 1981-03-05
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Granted: 1982-06-15
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Expires: 2001-03-05
Abstract
Abstract A method of electrically isolating a plurality of semiconductor integrated circuit components and for forming gate elements for silicon gate transistors is disclosed whereby extremely narrow line widths can be formed which heretofore have been unattainable by practicing conventional photolithography.
Inventors
- 👤 Dale T. Trenary
- 👤 Allen H. Frederick
- 👤 Robert M. Whelton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 01:13
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; Y; Y10; Y10S; Y10S148/00; Y10S148/05; Y10S148/111; Y10S148/143; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
97 words
A method of forming a narrow gate upon a semiconductor body comprising: A. forming a first masking layer upon the semiconductor body; B. forming a second masking layer upon the first masking layer; C. forming a retro-etched area by partially retro-etching the first masking layer below the second masking layer; D. substantially filling said retro-etched area with a material forming the narrow gate; and E. removing the first and second masking layers and material in non-retro-etched area leaving behind on said semiconductor body, only said material in the form of a narrow gate in said retro-etched area.
Claim 2
Independent Claim
97 words
A method of forming a narrow gate upon a semiconductor body comprising: A. forming a first masking layer upon the semiconductor body; B. forming a second masking layer upon the first masking layer; C. forming a retro-etched area by partially retro-etching the first masking layer below the second masking layer; D. substantially filling said retro-etched area with a material forming the narrow gate; and E. removing the first and second masking layers and material in non-retro-etched area leaving behind on said semiconductor body, only said material in the form of a narrow gate in said retro-etched area.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein said first masking layer comprises silicon dioxide.
Claim 4
Dependent Claim
13 words
The method of claim 1 wherein said second masking layer comprises silicon nitride.
Claim 5
Dependent Claim
15 words
The method of claim 1 wherein the material substantially filling the retro-etched area comprises polysilicon.
Claim 6
Dependent Claim
21 words
The method of claim 1 which further comprises diffusing a dopant into the semiconductor body in areas adjacent the retro-etched area.
Claim 7
Independent Claim
118 words
A method of forming a MOS transistor within a silicon body comprising: A. forming a silicon dioxide layer upon the silicon body; B. forming a silicon nitride layer upon the silicon dioxide layer; C. forming a retro-etched area by etching the silicon dioxide layer to a predetermined area under the silicon nitride layer; D. forming a polysilicon layer over the silicon body to substantially fill the retro-etched area; E. removing the polysilicon as applied in step D except in the retro-etched area; F. removing the remaining silicon nitride; G. removing all silicon dioxide in the areas not covered by the polysilicon; and H. diffusing a dopant into the silicon body in the areas not covered by the polysilicon.
Claim 8
Independent Claim
118 words
A method of forming a MOS transistor within a silicon body comprising: A. forming a silicon dioxide layer upon the silicon body; B. forming a silicon nitride layer upon the silicon dioxide layer; C. forming a retro-etched area by etching the silicon dioxide layer to a predetermined area under the silicon nitride layer; D. forming a polysilicon layer over the silicon body to substantially fill the retro-etched area; E. removing the polysilicon as applied in step D except in the retro-etched area; F. removing the remaining silicon nitride; G. removing all silicon dioxide in the areas not covered by the polysilicon; and H. diffusing a dopant into the silicon body in the areas not covered by the polysilicon.
Claim 9
Dependent Claim
18 words
The methods of claim 6 wherein the width of the retro-etched area is less than approximately 20,000 A.
Claim 10
Dependent Claim
22 words
The method of claim 6 wherein a thin layer of silicon dioxide is present in the retro-etched area on the silicon body.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-14 | 1985-12-14 | 1986-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-14 | 1989-12-14 | 1990-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-14 | 1993-12-14 | 1994-06-15 | $7700.00 | Window Closed / Lapsed |