Patent US2898593A successfully refreshed from Google Patents.
Patent US4334347A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4334347A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming an improved gate member for a gate injected floating gate memory device

Assignee: Intersil Corp
•
Filing: 1980-08-06
•
Granted: 1982-06-15
•
Expires: 2000-08-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An improved gate injected, floating gate memory device is described having improved charge retention and endurance characteristics is described in which the barrier height for the injection of charge (electrons or holes) into the floating gate is reduced. This is accomplished by utilizing a layer of semi-insulating polycrystalline silicon between the control electrode and the insulating layer over the floating gate.

Inventors

  • 👤 Norman Goldsmith
  • 👤 Sheng T. Hsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 07:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/682; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 165 words
In a process for forming a floating gate storage device, the device having: a. a body of semiconductor material with a pair of semiconductor regions of a first conductivity type embeded therein and spaced a given distance one from the other; b. an intermediate semiconductor region of opposite conductivity type defining the space between the pair of regions; and c. a floating gate structure having a floating gate member disposed over the intermediate region and insulated therefrom and a control gate member disposed over the floating gate member and insulated therefrom; an improved method of forming the gate structure, comprising the steps of: growing a first insulating layer over at least the intermediate region; forming a floating gate member on the first insulating layer over the intermediate region; growing a second insulating layer over the gate member and the first insulating layer; depositing a layer of semi-insulating polycrystalline silicon over the second insulating layer; and depositing a conductive control gate member over the semi-insulating layer.
Claim 2
Dependent Claim 165 words
In a process for forming a floating gate storage device, the device having: a. a body of semiconductor material with a pair of semiconductor regions of a first conductivity type embeded therein and spaced a given distance one from the other; b. an intermediate semiconductor region of opposite conductivity type defining the space between the pair of regions; and c. a floating gate structure having a floating gate member disposed over the intermediate region and insulated therefrom and a control gate member disposed over the floating gate member and insulated therefrom; an improved method of forming the gate structure, comprising the steps of: growing a first insulating layer over at least the intermediate region; forming a floating gate member on the first insulating layer over the intermediate region; growing a second insulating layer over the gate member and the first insulating layer; depositing a layer of semi-insulating polycrystalline silicon over the second insulating layer; and depositing a conductive control gate member over the semi-insulating layer.
Claim 3
Dependent Claim 52 words
The method according to claim 1, comprising the further step: depositing the semi-insulating layer as a graded layer having an excess of silicon atoms and a minimum of oxygen atoms adjacent the control gate member and an excess of oxygen atoms and a minimum of silicon atoms adjacent the second insulating layer.
Claim 4
Dependent Claim 87 words
The process according to claim 2, wherein the step of depositing the semi-insulator layer comprises: depositing the semi-insulating layer as a plurality of sublayers, each sublayer having a different ratio of silicon and oxygen atoms therein; the sublayer adjacent the control gate member being deposited with the highest level of silicon atoms and the lowest level of oxygen atoms; the sublayer adjacent the second insulating layer of the floating gate member being deposited with the highest level of oxygen atoms and the lowest level of silicon atoms.
Claim 5
Dependent Claim 22 words
The process according to claim 3, wherein: the body of semiconductor material is an island of silicon formed on an insulative substrate.
Claim 6
Dependent Claim 23 words
The process according to claim 4, wherein: the insulative substrate is selected from the group consisting of sapphire, spinel and monocrystalline beryllium oxide.
Claim 7
Dependent Claim 20 words
The process according to claim 3, wherein: the body of semiconductor material is bulk silicon of the opposite type conductivity.

References Cited (Backward Citations)

US3649884A Cited
US3868187A Cited
US3836992A Cited
US4115914A Cited
US4057820A Cited
US4119995A Cited
US4119995B1 Cited
US4104675A Cited
US4162504A Cited
US4217601A Cited
US4253106A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-06-14 1985-12-14 1986-06-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-06-14 1989-12-14 1990-06-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-06-14 1993-12-14 1994-06-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag