Synchronization system for digital data

Claim 2

A digital signal synchronization system comprising: a signal source for supplying an input signal; an analog to digital converter having an input connected to said signal source; and an output; a plurality of substantially identical summing circuits each connected to said output of said analog to digital converter for summing a plurality of successive signals for a predetermined time; a plurality of clock sources each connected to a corresponding one of said summing circuits so that each summing circuit begins summing said digital signal beginning at a different time; and decision means connected to the output of each of said summing circuits for selecting one of said summing circuits according to a predetermined criteria, so that said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal.

Claim 3

A system as defined in claim 1, wherein said decision means functions to select said one of said summing circuits having the output with the greatest absolute value.

Claim 4

A system as defined in claim 1, when said summing circuits comprises an adder and a shifter register memory.

Claim 5

A system as defined in claim 1, wherein each of said clock sources has a frequency identical with the digital data rate of the input signal.

Claim 6

A system as defined in claim 1, wherein each of said clock sources has a different phase.

Claim 7

A digital signal synchronization system comprising: a signal source for supplying an input signal; an analog to digital converter having an input connected to said signal source; and an output; a plurality of substantially identical summing circuits each connected to said output of said analog to digital convertor for summing a plurality of successive signals for a predetermined time; a plurality of clock sources each connected to a corresponding one of said summing circuits so that each summing circuit begins summing said digital signal beginning at a different time; decision means connected to the output of each of said summing circuits for selecting one of said summing circuits according to a predetermined criteria so that said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal; and said summing circuits comprise an adder and a shift register memory.

Claim 8

A digital signal synchronization system comprising: a signal source for supplying an input signal; an analog to digital converter having an input connected to said signal source; and an output; a plurality of substantially identical summing circuits each connected to said output of said analog to digital convertor for summing a plurality of successive signals for a predetermined time; a plurality of clock sources each connected to a corresponding one of said summing circuits so that each summing circuit begins summing said digital signal beginning at a different time; decision means connected to the output of each of said summing circuits for selecting one of said summing circuits according to a predetermined criteria so that said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal; and said summing circuits comprise an adder and a shift register memory.

Claim 9

A system as defined in claim 6, wherein said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal.

Claim 10

A system as defined in claim 6, wherein each of said clock sources has a frequency identical with the digital data rate of the input signal.

Claim 11

A system as defined in claim 6, wherein each of said clock sources has a different phase.

Claim 12

A digital signal synchronization system comprising: a digital signal source for supplying an input digital signal; a plurality of substantially identical integrating circuits each connected to said digital signal source for integrating the signal for a predetermined time; a plurality of clock sources each connected to a corresponding one of said integrating circuits so that each integrating circuit begins integrating said digital signal at a different time; and decision means connected to the output of each of said integrating circuits for selecting one of said integrating circuits such that said clock signal associated with said one of said integrating circuits is the synchronized clock signal associated with said input digital signal.

Claim 13

A digital signal synchronization system comprising: a digital signal source for supplying an input digital signal; a plurality of substantially identical integrating circuits each connected to said digital signal source for integrating the signal for a predetermined time; a plurality of clock sources each connected to a corresponding one of said integrating circuits so that each integrating circuit begins integrating said digital signal at a different time; and decision means connected to the output of each of said integrating circuits for selecting one of said integrating circuits such that said clock signal associated with said one of said integrating circuits is the synchronized clock signal associated with said input digital signal.

Claim 14

A system as defined in claim 10, wherein said decision means functions to select said one of said integrating circuits having the output with the greatest absolute value.

Claim 15

A system as defined in claim 10, when said integrating circuits comprises integrate and dump matched filters.

Claim 16

A system as defined in claim 10, wherein each of said clock sources has a frequency identical with the data rate of the input digital signal.

Claim 17

A system as defined in claim 10, wherein each of said clock sources has a different phase.

Claim 18

A system as defined in claim 10, further comprising convolving means connected to the output of said selected one of said integrating circuits for computing a convolution function signal using the output signal on said output.

Claim 19

A system as defined in claim 10, further comprising threshold detection means connected to the output of said selected one of said integrating circuits for sensing the output signal on said output and producing an activating signal if the magnitude of said output signal exceeds a predetermined threshold signal magnitude.

Claim 20

A system as defined in claim 10, wherein said integrating circuit comprises a serial memory for storing a plurality of words in information representing the successive integrations of said input signal.