Patent US4325129A successfully refreshed from Google Patents.
US4325129A
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Non-linear logic module for increasing complexity of bit sequences
Assignee: Motorola Solutions Inc
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Filing: 1980-05-01
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Granted: 1982-04-13
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Expires: 2000-05-01
Abstract
Abstract A logic system for implementation of a feed-forward non-linear generator for producing a plurality of programmable complex sequences from an input bit stream.
Inventors
- 👤 Edward J. Groth, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:05
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K3/00; H03K3/84
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
149 words
A non-linear digital generator circuit for producing controllably complex bit sequences comprising in combination: a plurality of shift registers each being of predetermined bit length, each of said plurality of shift registers comprising: a first segmented portion being controllable as to a bit delay length between an input thereto and an output thereof; and a second segmented portion having a fixed bit length for implementing a predetermined span between an input thereto and an output thereof, said input being derived from said output of said first segmented portion; means for controlling said bit length of each of said plurality of first segmented portions of said plurality of shift registers; a plurality of means for combining said inputs and outputs of each of said second segmented portions, each of said combining means having an output thereof; and means for modulo-two adding said outputs of said plurality of said combining means.
Claim 2
Dependent Claim
149 words
A non-linear digital generator circuit for producing controllably complex bit sequences comprising in combination: a plurality of shift registers each being of predetermined bit length, each of said plurality of shift registers comprising: a first segmented portion being controllable as to a bit delay length between an input thereto and an output thereof; and a second segmented portion having a fixed bit length for implementing a predetermined span between an input thereto and an output thereof, said input being derived from said output of said first segmented portion; means for controlling said bit length of each of said plurality of first segmented portions of said plurality of shift registers; a plurality of means for combining said inputs and outputs of each of said second segmented portions, each of said combining means having an output thereof; and means for modulo-two adding said outputs of said plurality of said combining means.
Claim 3
Dependent Claim
21 words
The circuit according to claim 1 further comprising an optional input to said modulo-two adding means for inputting a bit string.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-12 | 1985-10-12 | 1986-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-12 | 1989-10-12 | 1990-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-12 | 1993-10-12 | 1994-04-13 | $7700.00 | Window Closed / Lapsed |