Nonlinear nonsingular feedback shift registers

Claim 2

An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r where r > OR = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including a first AND gate for providing an output which is the AND function of the assertion outputs of all the first (r-1) stages, a second AND gate for providing an output which is the AND function of the negation outputs of all the first (r-1) stages, a third AND gate for providing an output which is the AND function of the outputs of the first (r-1) stages, one output per stage, where at least one output is an assertion output and at least one output is a negation output, and modulo-2 summing means for providing a feedback output which is the modulo-2 sum of the outputs of said first through third AND gates and the assertion outputs of stages defined by the exponents of terms in a characteristic polynomial fo(x) phi r 1(x), where phi r 1(x) represents a primitive polynomial of degree r-1; and means for feeding back said feedback output to said first stage.

Claim 3

An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r, where r > or = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including a single AND gate for providing an output which is the AND function of the outputs of said (r-1) stages, one output from each stage, where the type of output of each stage following the first stage is opposite the type of output of the preceding stage, and modulo-2 summing means for providing a feedback output which is the modulo-2 sum of the oeutput of said AND gate and the complement of the modulo-2 sum of the assertion outputs of stages defined by the exponents of a characteristic polynomial fo(x) (1+x) phi r 1(x), where phi r 1(x) is a primitive polynomial of degree r-1; and means for feeding back said feedback output to said first stage.

Claim 4

An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r, where r > or = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including a single AND gate for providing an output which is the AND function of the outputs of said (r-1) stages, one output from each stage, where the type of output of each stage following the first stage is opposite the type of output of the preceding stage, and modulo-2 summing means for providing a feedback output which is the modulo-2 sum of the oeutput of said AND gate and the complement of the modulo-2 sum of the assertion outputs of stages defined by the exponents of a characteristic polynomial fo(x) (1+x) phi r 1(x), where phi r 1(x) is a primitive polynomial of degree r-1; and means for feeding back said feedback output to said first stage.

Claim 5

The shift register as described in Claim 2 wherein the output of the AND gate is a function of the assertion outputs of all the odd-numered stages of said (r-1) stages and the negation outputs of all the even-numbered stages of said (r-1) stages.

Claim 6

The shift register as described in claim 2 wherein the outPut of the AND gate is a function of the negation outputs of all the odd-numered stages of said (r-1) stages and the assertion outputs of all the even-numbeered stages of said (r-1) stages.

Claim 7

An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r, where r > or = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including an AND gate for providing an output which is the AND function of outputs of the first (r-1) stages, one output per stage, the outputs being alternating pairs of assertion and negation outputs, with the output of the first stage being a negation output followed by the negation output of the second stage and thereafter by alternating pairs of assertion and negation outputs up to (r-1) outputs, or the output of the first stage being an assertion output followed by alternating pairs of negation and assertion outputs up to (r-1) outputs, or the outputs of the first two stages being the assertion outputs followed by alternating pairs of negation and assertion outputs up to (r-1) outputs, or the first stage output is the negation output followed by alternating pairs of assertion and negation outputs up to (r-1) outputs, and modulo-2 summing means for modulo-2 summing the AND gate output and selected outputs of said states to provide a feedback output which is the complement of the modulo-2 sum of said AND gate output and assertion outputs of stages defined by the exponents of terms of a characteristic polynomial, definablle as fo(x) (1+x)2 phi r 2(x), where phi r 2(x) is a primitive polynomial of degree r-2.

Claim 8

An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r, where r > or = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including an AND gate for providing an output which is the AND function of outputs of the first (r-1) stages, one output per stage, the outputs being alternating pairs of assertion and negation outputs, with the output of the first stage being a negation output followed by the negation output of the second stage and thereafter by alternating pairs of assertion and negation outputs up to (r-1) outputs, or the output of the first stage being an assertion output followed by alternating pairs of negation and assertion outputs up to (r-1) outputs, or the outputs of the first two stages being the assertion outputs followed by alternating pairs of negation and assertion outputs up to (r-1) outputs, or the first stage output is the negation output followed by alternating pairs of assertion and negation outputs up to (r-1) outputs, and modulo-2 summing means for modulo-2 summing the AND gate output and selected outputs of said states to provide a feedback output which is the complement of the modulo-2 sum of said AND gate output and assertion outputs of stages defined by the exponents of terms of a characteristic polynomial, definablle as fo(x) (1+x)2 phi r 2(x), where phi r 2(x) is a primitive polynomial of degree r-2.

Claim 9

The shift register as described in claim 5 wherein the AND gate output is a function of the negation output of said first stage.

Claim 10

The shift register as described in claim 6 wherein the AND gate output is a function of the negation outputs of said first and second stages followed by alternating pairs of assertion and negation outputs up to (r-1) outputs.

Claim 11

The shift register as described in claim 6 wherein the AND gate output is a function of the negation output of the first stage followed by alternating pairs of assertion and negation outputs up to (r-1) outputs.

Claim 12

The shift register as described in claim 5 wherein the AND gate output is a function of the assertion output of said first stage.

Claim 13

The shift register as described in claim 9 wherein the AND gate output is a function of the assertion output of said first stage followed by alternating pairs of negation and assertion outputs up to (r-1) outputs.

Claim 14

The shift register as described in claim 9 wherein the AND gate output is a function of the assertion outputs of the first two stages, followed by alternating pairs of negation and assertion outputs up to (r-1) outputs.

Claim 15

An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r where r > or = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including first, second and third AND gates each responsive to a different combination of (r-1) outputs, one from each of the first (r-1) stages, for providing an output which the AND function of the output supplied thereto, said fiRst AND gate being responsive to a succession of (r-1) outputs in which every other output is an assertion output and every other output is a negation output, with the output of the first stage being either an assertion output or a negation output, said second AND gate being responsive to a succession of (r-1) outputs in which groups of three negation outputs followed by a single assertion output are repeated successively, with the output of the first stage being any of the three negation outputs or the assertion output, said third AND gate being responsive to a succession of (r-1) outputs in which groups of three assertion outputs followed by a single negation output are repeated successively, with the output of the first stage being any one of the three assertion outputs or the negation output, and modulo-2 summing means for providing a feedback output which is the complement of the modulo-2 sum of the outputs of said first, second and third gates and the assertion outputs of stages defined by the exponents of the terms of a characteristic polynomial fo(x) (1+x)3 phi r 3(x) where phi r 3(x) defines a primitive polynomial of degree r-3; and means for feeding back said feedback output to the first stage of said register.

Claim 16

An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r where r > or = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including first, second and third AND gates each responsive to a different combination of (r-1) outputs, one from each of the first (r-1) stages, for providing an output which the AND function of the output supplied thereto, said fiRst AND gate being responsive to a succession of (r-1) outputs in which every other output is an assertion output and every other output is a negation output, with the output of the first stage being either an assertion output or a negation output, said second AND gate being responsive to a succession of (r-1) outputs in which groups of three negation outputs followed by a single assertion output are repeated successively, with the output of the first stage being any of the three negation outputs or the assertion output, said third AND gate being responsive to a succession of (r-1) outputs in which groups of three assertion outputs followed by a single negation output are repeated successively, with the output of the first stage being any one of the three assertion outputs or the negation output, and modulo-2 summing means for providing a feedback output which is the complement of the modulo-2 sum of the outputs of said first, second and third gates and the assertion outputs of stages defined by the exponents of the terms of a characteristic polynomial fo(x) (1+x)3 phi r 3(x) where phi r 3(x) defines a primitive polynomial of degree r-3; and means for feeding back said feedback output to the first stage of said register.

Claim 17

The shift register as described in claim 12 wherein said modulo-2 summing means are responsive to one output of each of the stages defined by the exponents of the terms of said characteristic polynomial, all of the outputs of the defined stages being assertion outputs except one which is the negation output.

Claim 18

The shift register as described in claim 13 wherein each of said first, second and third gates is responsive to the negation output of said first stage.

Claim 19

The shift register as described in claim 13 wherein each of said first, second and third AND gates is responsive to the assertion output of said first stage.

Claim 20

The shift register as described in claim 12 wherein said first AND gate is responsive to the assertion output and at least said second or said third AND gate is responsive to a negation output of said first stage.

Claim 21

The shift register as described in claim 16 wherein said second AND gate is responsive to the negation output of said first stage.

Claim 22

The shift register as described in claim 16 wherein said third AND gate is responsive to the negation output of said first stage.

Claim 23

The shift register as described in claim 12 wherein said first AND gate is responsive to the negation output of said first stge and at least said second or said third gate is responsive to the assertion output of said first stage.

Claim 24

The shift register as described in claim 19 wherein each of said second and third AND gates is responsive to the assertion output of said first stage.