Patent US4323730A successfully refreshed from Google Patents.
US4323730A
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Idle channel noise suppressor for speech encoders
Assignee: Nortel Networks Ltd
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Filing: 1979-06-13
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Granted: 1982-04-06
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Expires: 1999-06-13
Abstract
Abstract The idle channel for a speech encoder is detected by the detection, at the encoder comparator output, of zero-level traversals caused by noise transient signals appearing at the analog input of the encoder. In response to the detection of an idle channel, the encoder is caused to output a PCM code sample corresponding to a zero amplitude analog signal. In order that a speech signal passing through zero amplitude during the sampling period not be confused with an idle channel condition, the detection circuit responds only to a plurality of zero-level traversals.
Inventors
- 👤 Anthony K. D. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:24
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
112 words
In a circuit for encoding analog signals into pulse code modulation samples, the encoding circuit comprising an analog comparator circuit responsive to an analog signal and to a reference signal to provide a first signal, a method for recognizing an idle channel during a sampling period, comprising the steps of: counting at least two, and not more than thirty two, zero-level traversals by the signal at the output of the analog comparator circuit during a single sampling period, and storing in a register means a signal indicating the presence of said traversals whereby the encoding circuit is caused to output a pulse code modulation word corresponding to a zero amplitude analog signal.
Claim 2
Dependent Claim
112 words
In a circuit for encoding analog signals into pulse code modulation samples, the encoding circuit comprising an analog comparator circuit responsive to an analog signal and to a reference signal to provide a first signal, a method for recognizing an idle channel during a sampling period, comprising the steps of: counting at least two, and not more than thirty two, zero-level traversals by the signal at the output of the analog comparator circuit during a single sampling period, and storing in a register means a signal indicating the presence of said traversals whereby the encoding circuit is caused to output a pulse code modulation word corresponding to a zero amplitude analog signal.
Claim 3
Dependent Claim
125 words
In a circuit for encoding analog signals into pulse code modulation samples, the encoding circuit comprising an analog comparator circuit responsive to an analog signal and to a reference signal to provide a first signal, and a first circuit means responsive to the first signal for providing a pulse code modulation sample representative of the amplitude of the analog sample, a method for suppressing idle channel noise, comprising the steps of: counting at least two, not more than thirty two, zero level traversals by the signal at the output of the analog comparator circuit during a single sampling period and in response to a predetermined count, causing the first circuit means to output a pulse code modulation word representative of a zero amplitude analog signal.
Claim 4
Dependent Claim
125 words
In a circuit for encoding analog signals into pulse code modulation samples, the encoding circuit comprising an analog comparator circuit responsive to an analog signal and to a reference signal to provide a first signal, and a first circuit means responsive to the first signal for providing a pulse code modulation sample representative of the amplitude of the analog sample, a method for suppressing idle channel noise, comprising the steps of: counting at least two, not more than thirty two, zero level traversals by the signal at the output of the analog comparator circuit during a single sampling period and in response to a predetermined count, causing the first circuit means to output a pulse code modulation word representative of a zero amplitude analog signal.
Claim 5
Dependent Claim
159 words
In a circuit for encoding analog signals into pulse code modulation samples, the encoding circuit comprising an analog comparator circuit responsive to an analog signal and to a reference signal for providing a first signal, and a first circuit means, including a buffer register, responsive to the first signal for generating and storing in said buffer register a pulse code modulation sample representative of the amplitude of the analog sample, a circuit for suppressing idle channel noise, comprising: a detector register circuit; a counter circuit responsive to at least two, and not more than thirty two, zero-level traversals by the signal at the output of the analog comparator circuit during a single sampling period for storing in the detector register circuit a signal indicating the presence of said traversals, the output of said detector register circuit providing an inhibit signal for causing said buffer register to store a pulse code modulation sample representative of a zero amplitude analog signal.
Claim 6
Dependent Claim
159 words
In a circuit for encoding analog signals into pulse code modulation samples, the encoding circuit comprising an analog comparator circuit responsive to an analog signal and to a reference signal for providing a first signal, and a first circuit means, including a buffer register, responsive to the first signal for generating and storing in said buffer register a pulse code modulation sample representative of the amplitude of the analog sample, a circuit for suppressing idle channel noise, comprising: a detector register circuit; a counter circuit responsive to at least two, and not more than thirty two, zero-level traversals by the signal at the output of the analog comparator circuit during a single sampling period for storing in the detector register circuit a signal indicating the presence of said traversals, the output of said detector register circuit providing an inhibit signal for causing said buffer register to store a pulse code modulation sample representative of a zero amplitude analog signal.
Claim 7
Dependent Claim
15 words
A circuit as defined in claim 3 wherein the counter circuit is a three-stage counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-05 | 1985-10-05 | 1986-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-05 | 1989-10-05 | 1990-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-05 | 1993-10-05 | 1994-04-06 | $7700.00 | Window Closed / Lapsed |