Voice versus pulsed tone signal discrimination circuit

Claim 2

A voice signal discriminating circuit for discriminating a voice signal on a line from standard busy signals and dial tones on said line, said circuit comprising, envelope signal generating means responsive to audio frequency signals on said line for generating peak envelope signals having an amplitude which follows the peak amplitude of said audio frequency signals, switching means responsive to variations in the amplitude of said peak envelope signal for switching between a first stage and a second state in response to cyclic variations of the amplitude of said peak envelope signal, counter summation means connected to said switching means for counting, when enabled, the number of cyclic switchings of said switching means, time period control means for enabling and resetting said counter summation means for pre-established time periods, and output means connected to said counter summation means for producing an indication at the output thereof, signifying that a voice signal is on said line, when the count accumulated by said counter summation means reaches a predetermined number.

Claim 3

A voice signal discriminating circuit as claimed in claim 1 wherein said signal time period control means, comprises, a counter timer having a plurality of stages for registering the number of pulses counted thereby and pulse generating means connected to said counter timer for applying pulses to an input thereof.

Claim 4

A voice signal discriminator circuit as claimed in claim 2, wherein said envelope signal generating means comprises, a coupling means for coupling signals on said line into said discriminator circuit, means for rectifying the signals coupled into said circuit to provide rectified signals, smoothing circuit means for following the peaks of audio frequency signals applied thereto, and said rectified signals applied to said smoothing circuit means to provide an output signal which has an amplitude which substantially follows the peak amplitude of said rectified signals.

Claim 5

A voice signal discriminator circuit as claimed in claim 3 wherein said counter summer comprises, a plurality of counting stages, each having a reset/enabling terminal.

Claim 6

A voice signal discriminator circuit as claimed in claim 4 wherein said time period control means further comprises logic circuit means, connected between the output terminals of stages of said counter timer and the reset/enabling terminals of the stages of said counter summer, for controlling the enablement and resetting of said counter summer in dependence upon the count in said pulse counter.

Claim 7

A voice signal discriminating circuit for discriminating a voice signal on a line from standard busy signals and dial tones on said line, said circuit comprising, counter summation means for counting, when enabled, the number of cycles of any audio signal coupled thereto, said counter summation means comprising a plurality of counting stages, each having a reset/enablement terminal, coupling means for connecting audio signals on said line to said counter summation means, smoothing and rectifying circuit means connected to said coupling means for generating an actuating control signal when an audio signal is on said line, and time period control means connected to said smoothing and rectifying circuit means and to said counter summation means for enabling said counter summation means for a predetermined period which begins a fixed period after initiation of said actuating control signal, said fixed period being long enough to prevent enablement of said counter summation means during the rise time of a busy signal and dial tone, and output means connected to said counter summation means for producing an indication at the output thereof, signifying that a voice signal is on said line, when the count accumulated by said counter summation means reaches a predetermined number.

Claim 8

A voice signal discriminating circuit for discriminating a voice signal on a line from standard busy signals and dial tones on said line, said circuit comprising, counter summation means for counting, when enabled, the number of cycles of any audio signal coupled thereto, said counter summation means comprising a plurality of counting stages, each having a reset/enablement terminal, coupling means for connecting audio signals on said line to said counter summation means, smoothing and rectifying circuit means connected to said coupling means for generating an actuating control signal when an audio signal is on said line, and time period control means connected to said smoothing and rectifying circuit means and to said counter summation means for enabling said counter summation means for a predetermined period which begins a fixed period after initiation of said actuating control signal, said fixed period being long enough to prevent enablement of said counter summation means during the rise time of a busy signal and dial tone, and output means connected to said counter summation means for producing an indication at the output thereof, signifying that a voice signal is on said line, when the count accumulated by said counter summation means reaches a predetermined number.

Claim 9

A voice signal discriminating circuit as claimed in claim 6 wherein said time period control means comprises, a pulse counter, having a plurality of stages, for counting pulses applied thereto, pulse generating means for generating a series of pulses, logic circuit means, connected between the outputs of stages of said pulse counter and the reset/enabling terminals of the stages of said counter summation means, for holding said counter summation means reset when said pulse counter is disabled, during a first predetermined number of initial counts of said pulse counter, and after a second predetermined number of counts of said pulse counter, and for alternatively enabling and resetting said counter summation means during said second predetermined number of counts of said pulse counter.

Claim 10

A voice signal discriminating circuit as claimed in claim 7 wherein said logic means is also connected to said pulse generating means and wherein the duration of said pulses from said pulse generating means determines the duration of continuous enablement of said counter summation means.